Jan Müller

Real-time mixes: a bandwidth-efficient anonymity protocol

We present techniques for efficient anonymous communication with real-time constraints as necessary for services like telephony, where a continuous data stream has to be transmitted. For concreteness, we present the detailed protocols for the narrow-band ISDN (integrated services digital network), although the heart of our techniques-anonymous channels-can also be applied to other networks. For ISDN, we achieve the same data rate as without anonymity, using the same subscriber lines and without any significant modifications to the long-distance network. A precise performance analysis is given. Our techniques are based on mixes, a method for anonymous communication for e-mail-like services introduced by D. Chaum (1981).

OPTIMAL SOFTWARE PIPELINING UNDER RESOURCE CONSTRAINTS

In this paper we present a novel approach to find an optimum loop schedule under consideration of limited resources. The initiation interval λ is assumed to be a rational number. Our approach is formulated as a single optimization problem that can be solved using integer linear programming. The objective is to minimize the initiation interval, while both numerator and denominator of λ can be incorporated as variables of the optimization problem. the resources (functional units) may have a pipeline architecture; the approach also supports heterogeneous functional units.

NERO mastering 300k CNN cells

A novel massively-parallel fine-grain architecture featuring a digital emulation of Cellular Nonlinear Networks (CNN) is presented. A virtual cellular network is processed line-by-line by a locally connected linear array of processing elements. The resulting computing system is able to execute complex CNN program code consisting of consecutive operations. Furthermore we present a scalable FPGA implementation of this architecture for currently up to 480 × 640 cells with a precision up to 18 bit.

CESAR: Emulating Cellular Networks on FPGA

Complex dynamical systems establish offer entirely new possibilities to the development of groundbreaking data processing methods. In the domains of image and video processing, locally coupled cellular array computers, based on Cellular Nonlinear Networks (CNN), accelerate the computation of large amounts of data in real-time, due to their inherent concept of massive parallelism. Current VLSI implementations however, are accompanied by several distinct drawbacks. The computational accuracy of most currently available systems is limited to 8 bit, and the volatilely capacitively stored state values of analogue realisations often lead to errors when multiple tasks are processed sequentially. Moreover, the systems hardly allow to run a CNN program code to provide the full functionality of a CNN-UM. In this contribution, the novel CESAR architecture is proposed for the digital emulation of a time-discrete CNN-UM. The programmable array computer facilitates the powerful computation of consecutive CNN operations and the cost-efficient implementation of several application-specific configurations with variable network size and data representation. The presented architecture retains the inherent parallel paradigm of CNN, and assigns one processing element to each cell of the network. The cell outputs are coupled and stored locally, thus minimising data exchange with external structures and maximising the computation speed. The internal fixed-point multiplications are accelerated by using on-chip DSP resources provided by current FPGAs. By this means, a CNN-based embedded system with 128 cells, a 3 × 3 neighbourhood and 18 bit data representation was implemented on a Xilinx Virtex-5 FPGA.

Optimal loop scheduling with register constraints using flow graphs

We present a novel loop scheduling approach using a generalized flow graph model of the resource constraints. From this model we derive a new flow graph to incorporate register constraints. Our linear programming implementation produces an optimum loop schedule, respecting the constraints on functional units and registers in a single optimization problem. Moreover, the iteration interval is treated as a rational number, and the approach supports heterogeneous processor architectures and pipelined functional units. Compared to earlier approaches, the solution can reduce the problem complexity and solution time, and provide faster loop schedules.

An Improved Cellular Nonlinear Network Architecture for Binary and Grayscale Image Processing

Cellular nonlinear networks (CNNs) constitute a very powerful paradigm for single instruction/multiple data computers with fine granularity. Analog and mixed-signal implementations have proven to be suitable for applications in high-speed image processing, robot control, medical signal processing, and many more. Especially digital emulations on field-programmable gate arrays (FPGAs) allow the development of general-purpose computers based on the CNN universal machine with an inherently parallel structure, a high degree of flexibility and a superior computational precision. However, these emulations turn out to be inefficient for the execution of binary operations, which account for more than two-thirds of all processing steps in a typical CNN algorithm. In this contribution, we present an architecture for the emulation of CNNs that supports both a fast and efficient processing of binary images, and a high computational accuracy when needed. With the FPGA implementation of this architecture, a speed-up factor of up to 5 is achieved for binary-data operations.

NEROvideo: a general-purpose CNN-UM video processing system

Emulations of cellular nonlinear networks (CNN) on digital reconfigurable hardware have proved to be adequate for highly-efficient computation of massive data, exceeding the accuracy and flexibility of full-custom designs. Based on a recently-proposed architecture for the emulation of a large-scale CNN universal machine, a new real-time video processing system has been developed. Due to its free programmability and massively-parallel architecture the system is very suitable for high-speed computation of complex algorithms that follow the idea of spatio-temporal computing. Implemented on a state-of-the-art Xilinx Zynq system-on-chip, the proposed setup is capable of processing a

A Hardware–Software System for Tomographic Reconstruction

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