Jan Van Campenhout

Circuit-level simulation approach to analyze system-level behavior of VCSEL-based optical interconnects

In order to satisfy the increasing demand for interchip interconnect bandwidth, a number of current research projects are concentrating on the use of waveguided optical interconnect arrays to span PCB-range distances. To accelerate system design and technology development, CAD tools for the design and the simulation of the interconnects are indispensable. We are developing a design methodology for optical inter-chip interconnects, to produce a tool for assisting system designers on deciding on product and parameter options for the different interconnect building blocks. A mandatory first step in this methodology development concerns the investigation of the combined impact of individual product and parameter variations on system-level interconnect system properties. Accurately predicting some interconnect properties requires analog simulation of the full electrical-optical-electrical links. Detailed models for the link building blocks involving geometrical calculations are much too slow for this purpose. Circuit-level simulation tools, with appropriate model descriptions, are much more suitable. In this paper, we describe our framework for the joint simulation of the entire optical interconnect with a mixed analog/digital system. We discuss in detail a number of issues that are involved with the implementation of circuit-level simulation models in the analog modelling language Verilog-AMS, and show a link simulation example.

Reconfigurable optical interconnects for parallel computer systems: design space issues

In highly parallel computer systems, reconfigurable interconnect network topologies can improve the performance by adaptively increasing the communication bandwidth where it is most needed. In electrical reconfigurable interconnect networks (e.g. crossbars or multi-stage networks), a high reconfigurability can only be achieved at the cost of both chip area and network latency. The facts that short-distance optical link latencies are rapidly decreasing and that new technologies allow optical reconfigurability, make optical interconnects an interesting alternative to overcome these interconnection issues. Optical interconnection technologies indeed offer several possibilities to increase network connectivity without drastically increasing the chip area and the delay costs. In this paper we study the bandwidth and latency requirements of inter-processor and processor-memory interconnect for shared-memory parallel computers when the processor clock increases up to 10 GHz. We also investigate new enabling technologies and discuss their potential use in architectures based on reconfigurable optical interconnects.

Multi-channel free-space intra-chip optical interconnections: combining plastic micro-optical modules and VCSEL based OE-FPGA.

We fabricated and replicated in semiconductor compatible plastics a multichannel free-space optical interconnection module designed to establish intra-chip interconnections on an Opto-Electronic Field Programmable Gate Array (OE-FPGA). The micro-optical component is an assembly of a refractive lenslet-array and a high-quality microprism. Both components were prototyped using deep lithography with protons and were monolithically integrated using a vacuum casting replication technique. The resulting 16-channel module shows optical transfer efficiencies of 50% and interchannel crosstalks as low as -22 dB. These characteristics are sufficient to establish multichannel intra-chip interconnects with OE- FPGAs. The OE-FPGA we used was designed within a European co- founded MEL-ARI consortium, working towards a manufacturable solution for optical interconnects between CMOS ICs. The optoelectronic chip combines fully functional FPGA digital logic with the drivers, receivers and flip-chipped optoelectronic components. It features 2 optical inputs and 2 optical outputs per FPGA cell, amounting to 256 photonic I/O links based on multimode 980-nm VCSELs and InGaAs detectors.

Low-cost MOEM interconnect modules for Tb/s.cm2 aggregate bandwidth to Silicon chips

We report on the design, the fabrication, the characterization and the demonstration of scalable multi-channel free-space interconnection components with the potential for Tb/s.cm2 aggregate bit rate capacity over inter-chip interconnection distances. The demonstrator components are fabricated in a high quality optical plastic, PMMA, using an ion-based rapid prototyping technology that we call deep proton lithography. With the presently achieved Gigabit/s data rates for each of the individual 16 channels with a BER smaller than 10-13 and with inter-channel cross-talk lower than -22dB the module aims at optically interconnecting 2-D opto-electronic VCSEL and receiver arrays, flip-chip mounted on CMOS circuitry. Furthermore, using ray-tracing software and radiometric simulation tools, we perform a sensitivity analysis for misalignment and fabrication errors on these plastic micro-optical modules and we study industrial fabrication and material issues related to the mass- replication of these components through injection-molding techniques. Finally we provide evidence that these components can be mass-fabricated in dedicated, highly-advanced optical plastics at low cost and with the required precision.

Optical area I/O enhanced FPGA with 256 optical channels per chip

It is our goal to demonstrate the viability of massively parallel optical interconnections between electronic VLSI chips. This is done through the development of the technology necessary for the realization of such interconnections, and the definition of a systems architecture in which these interconnections play a meaningful role. Field-programmable gate arrays (FPGA) have been identified as a class of general-purpose very large scale integration components that could benefit from the massive introduction of state-of-the-art optical inter-chip interconnections at the logic level. In this paper, we present the realization of a small-scale optoelectronic FPGA with 8 X 8 logic cells, containing two optical sources and two receivers per FPGA cell yielding a total of 256 links per chip. These FPGA chips designed to operate with information rates of 80 Mbit/s/link will be used in a three- chip demonstrator system as a test bed for the concepts above. We first identify the reason why we think optical interconnects can provide added value in FPGAs. The next sections briefly discuss the general architecture of our demonstrator system and the realization of the optoelectronic FPGA. We then present first measurement results followed by ongoing work and conclusions.

Synchronization solutions for parallel short-range optical interconnect in mesochronous systems

As a result of the increasing complexity of electronic chips, the bandwidths required for inter- and intra-chip communication are rapidly increasing. As optoelectronics provides high-bandwidth and high-density interconnection it is considered as a candidate for short-range interconnection. For such interconnections, situated at a low level in the systems hierarchy, the interconnect latency is extremely critical for the systems performance. This paper describes some methods for mesochronous synchronization, needed for such interconnections. It will be shown that it can be beneficial to use an additional optical link to transfer a synchronization signal. Such a reference signal can be used efficiently for phase detection, provided that the data skew is sufficiently small, and result in a decrease of the cost-per-link.

Plastic micro-optical modules for VCSEL-based free-space intra-chip interconnections: demonstrator testbeds with OE-FPGAs

We fabricated and replicated in semiconductor compatible plastics a multi-channel free-space optical interconnection module designed to establish intra-chip interconnections on an Opto-Electronic Field Programmable Gate Array (OE-FPGA). The micro-optical component is an assembly of a refractive lenslet-array and a high-quality microprism. Both components were prototyped using deep lithography with protons and were monolithically integrated using a vacuum casting replication technique. The resulting 16 channel module shows optical transfer efficiencies of 50% and inter-channel cross-talks as low as 22 dB. These characteristics are sufficient to establish multi-channel intra-chip interconnects with OE-FPGAs. The OE-FPGA we used was designed within a European co-founded MEL-ARI consortium, working towards a manufacturable solution for optical interconnects between CMOS ICs. The optoelectronic chip combines fully functional FPGA digital logic with the drivers, receivers and flip-chipped optoelectronic components. With a careful alignment of the micro-optical free-space module above the OE-VLSI chip, we demonstrated for the first time to our knowledge multi-channel free-space intra-chip optical interconnections. Data-communication was achieved with 4 simultaneous channels working at 10Mb/s. The bitrate was limited by the chiptester. Furthermore we investigated the possibilities of a more advanced interconnection module prototyped by combining an in-house fabricated baseplate with microlenses and a commercially available micro 3D glass prism. With this approach the channel count is no longer limited by the thickness of the prism we can fabricate with deep lithography with protons. To conclude we report on the integration of this glass prism and our baseplate and on the first results obtained with this interconnection module.