Janaina Gonçalves Guimarães

Design of a Hamming neural network based on single-electron tunneling devices

In this paper, the first complete implementation of a Hamming neural network based on single-electron devices is presented. A large-scale network for character recognition simulation based on building block approach was successfully carried out. Simulations were done using SIMON and MATLAB softwares. Effects such as offset charges and dynamic behavior are taken into account. Moreover, room temperature operation is considered.

Nanoelectronic SET-based core for network-on-chip architectures

Abstract Nanoelectronics is a very promising step the world of electronics is taking. It is proved to be more efficient than the microelectronic approaches currently in use, mainly in terms of area and energy management. A Single-Electron Transistor (SET) is capable of confining electrons to sufficiently small dimensions, so that the quantization of both their charge and their energy is easily observable, making the SETs quantum mechanical devices. These features should allow building chips with a number of devices orders of magnitude greater than indicated by the roadmap still respecting area and power consumption restrictions. In this sense, Tera Scale Integrated (TSI) systems can be feasible in the future. A digital module, such as an arithmetic logic unit, completely implemented with SETs has already been proposed and validated by simulation. In this work a completely SET based network-on-chip (NoC) nanoelectronic core is proposed. Furthermore, a simple NoC architecture based on that nanoelectronic core is also evaluated. It is shown that the SET-based NoC has a promising performance considering parameters such as power consumption, area and clock frequency. A simple comparison of mesh NoC chip prototypes is shown.

Single-electron winner-take-all network

A winner-take-all (WTA) single-electron neuron is developed for the first time. This new single-electron circuit is proposed in order to implement a WTA neural network with lateral inhibition architecture. An expression for the neurons activation function is presented. Furthermore, a dot pattern recognition task is successfully performed by the implemented network considering effects such as offset charges and co-tunnelling.

Nanoelectronic content-addressable memory

A novel nanoelectronic single-electron content addressable memory is designed and simulated. The proposed memory has three important building blocks: a storage block, a comparison block and an addressing block. These building blocks were built based on single-electron circuits such as Reset-Set latches, exclusive-or gates and a WTA neural network. Each one of the building blocks was separately adjusted to provide room temperature operation before being connected together. Some analyses concerning stability of each block and of the whole memory circuit were made. The nanoelectronic memory was successfully validated by simulation.

Single-electron shift-register circuit

This work presents a 4-bit shift-register designed with single-electron tunneling devices. Firstly, a single-electron D flip-flop based on NAND gates was designed and simulated. Based on D flip-flops, the shift-register architecture was also designed and successfully simulated at room temperature. Some considerations about noise margin were made. Moreover, stability analyses for the SET NAND, SET D flip-flop and SET shift-register were carried out.

A signal processing system based upon monolithic neural coprocessors

A signal processing system based upon a custom-made neural coprocessor integrated circuit is presented. The system comprises a dedicated PCB containing up to four coprocessors, which works in association with a microcomputer. All control and communication software, including a program for neural network training, were also developed. A speech recognition application and a performance evaluation are also presented.

Carbon Nanotube Interconnects for Nanoelectronic Integrated Systems

A perspective study about the effect of carbon nanotube compared with copper interconnects in the H-tree distributed clock network - used for routing clock signals inside a chip - in nanoelectronic systems will be developed based on simulation models. Important features for circuit design, such as low logic level, high logic level, rise time, slew rate, attenuation, delay time, dissipated power and delay-power product will be evaluated by computer simulations. Results will show that distributed networks based on carbon nanotube interconnects are able to operate at terahertz frequencies.

Interconnect impact on the performance of a SET-based Network-on-Chip memory circuit

Generally, the memory module of a processor core occupies the most part of its area. In this sense, the power dissipation of that high density device module is an important issue for developing an integrated circuit, especially when considering the effects of dissipation due to interconnects. Nanoelectronic devices appear like an option for designing large integrated circuits, because of their lower power consumption compared to nowadays technologies. Among these nanoelectronic devices, single-electron transistors (SET) are known for their reduced area and power consumption features, which are orders of magnitude lower than CMOS devices. Taking that into account, this paper evaluates the performance of a SET-Memory based on NAND logic gates module considering the impact of non-ideal interconnects.