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Dive into the research topics where Jane W. Sowards is active.

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Featured researches published by Jane W. Sowards.


international integrated reliability workshop | 2010

Design-in reliability for over drive applications in advanced technology

Jae-Gyung Ahn; Ping-Chin Yeh; Jane W. Sowards; Nick Lo; Jonathan Chang

We present the FEOL reliability checking flow in advanced technology especially with over drive applications. We check gate bias values obtained from SPICE transient simulation against the maximum allowed value, Vg_max, to make sure robust gate dielectric reliability. We set up HSPICE MOSRA simulation procedure to let designers check the impact of BTI and HCI to each MOSFET device and the circuit performance at End-of-Lifetime (EOL). From HCI degradation analysis from HSPICE MOSRA, we obtained a good correlation between HCI damage and slew rate and conditions in which HCI degradation is negligible. We discuss on the selection of the stress conditions and monitor conditions to be checked. We applied HSPICE MOSRA to several over drive applications and were able to successfully justify them with careful modeling for HCI and NCHC in addition to BTI.


Archive | 2000

Nonvolatile/battery-backed key in PLD

Raymond C. Pang; Jennifer Wong; Scott O. Frake; Jane W. Sowards; Venu M. Kondapalli; F. Erich Goetting; Stephen M. Trimberger; Kameswara K. Rao


Archive | 2000

Programmable logic device with partial battery backup

Raymond C. Pang; Venu M. Kondapalli; Jane W. Sowards; Scott O. Frake; Jennifer Wong; F. Erich Goetting; Peter H. Alfke; Schuyler E. Shimanek


Archive | 2004

Programmable gate array and embedded circuitry initialization and processing

David P. Schultz; Stephen M. Douglass; Steven P. Young; Nigel G. Herron; Mehul R. Vashi; Jane W. Sowards


Archive | 1999

Structure and method for generating a clock enable signal in a PLD

Steven P. Young; Jane W. Sowards; Wilson K. Yee


Archive | 2009

Techniques for improving transistor-to-transistor stress uniformity

Jung-Ching J. Ho; Jane W. Sowards; Shuxian Wu


Archive | 2007

Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist

Jonathan Ho; Yan Wang; Xin X. Wu; Jane W. Sowards


Archive | 2008

Method and apparatus for improving a circuit layout using a hierarchical layout description

Peter Rabkin; Zhiyuan Wu; Min-Hsing Peter Chen; Jane W. Sowards; Michael J. Hart; Min-Fang Ho


Archive | 2007

Method and apparatus for modeling transistors in an integrated circuit design

Jane W. Sowards; Shuxian Wu; Kaiman Chan


Archive | 2002

Prediffuse programmable a logique d'interconnexion assurant le fonctionnement de circuit logique fixe integre

Stephen M. Douglass; Steven P. Young; Nigel G. Herron; Mehul R. Vashi; Jane W. Sowards

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