Janet M. Towner

Integrated Precision Polysilicon Resistors

Two problems were encountered in the manufacture of precision polysilicon resistors that related to resistance variations across the wafer. In our process, we use boron to counter dope the phosphorus rich n-polysilicon. The first problem encountered involved variation with a circular pattern; the highest resistances were in the center of the wafer. The characteristic pattern indicated the problem could relate to wafer charging during implant. Ultimately this problem was found not to relate to the implant. Good uniformity was obtained by moving the polysilicon anneal to a more innocuous location. A second problem was encountered following resolution of the first problem. Some wafers exhibited horizontal bands of constant resistance with the lowest values in the middle of the wafer. The problem was found to relate to photoresist outgassing and ion neutralization. This was resolved by restricting the process to an implanter with a large endstation, where emitted gases could be more effectively diluted.

Polysilicon Interface Engineering for Improved PIP Capacitors

The interpolysilicon oxide module has been a challenge for both intrinsic and extrinsic oxide quality. We are currently using two integration schemes. Our older technologies sequence the lightly doped drains, spacer oxide and source drain modules after gate etch but prior to oxide deposition. Conversely, in the newer technology the oxide and poly-2 depositions follow immediately after gate etch. The latter process has shown well-behaved failure distributions. This improvement is attributed to the poly-1 surface being protected against subsequent processing. A change in the process sequence is cost prohibitive considering the many high reliability customers who require automotive (ACQ) or medical (FDA) qualifications. Nonetheless, these same customers are driving toward zero defectivity (0 PPM).

The Effect of Wafer Substrate Resistance on Inter Poly Oxide Thickness Variation

In our mixed signal devices, deposited oxides are used in structures such as poly-poly capacitors. Wafers using highly doped substrates showed good thickness uniformity but uniformity deteriorated as the resistance of the substrate increased. Other factors that increased substrate resistance also increased nonuniformity. Thickness variation was correlated to electrostatic charge imparted to the wafer from poorly grounded wafer handling robotics. This charging likely caused plasma instabilities that promoted the absorption and reaction of the TEOS intermediates

Using Ion Implantation to Streamline High Volt Processing in Standard CMOS

In a standard 0.5 μm single well technology, a deep N‐well is constructed using a 150 keV P implant at a dose of 1e13 at/cm2 and driven to a final depth of 4 μm. To make this N‐well suitable for automotive battery applications it is constructed with 2 μm P‐tub enclosure. Use of a high energy (780 keV P+++) implant streamlined the requisite long diffusion cycle such that it could be processed in a standard diffusion drive. While this resulted in longer implant times, it reduced the overall cycle time for a low volume, high voltage custom devices.

Threshold Voltage Mismatch Resulting from Mechanical Vibration

A severe yield loss was experienced for several mixed‐signal devices which relied on matched transistor pairs in their operation. The loss was caused by abrupt variations in threshold voltage over the short distance that separated the transistors. To determine if the problem was caused by nonuniform dosing, the threshold voltage implant was performed in five parts with the wafer repositioned each time for fivefold symmetry. A significant yield improvement resulted from this change. The pattern of loss was also reproduced on test wafers. Root cause of the micrononuniformity was traced to excessive mechanical vibration of the source rough pump; this pump was located inside the enclosure to isolate it from ground. The vibration was transmitted to the wafer in the direction of the mechanical scan.

Novel Process Control by Measurement of Silicon Lattice Damage

In this work, a novel SPC monitor of RTP temperature was developed where measurements are made directly on product. This technique significantly reduces test wafer costs while allowing real-time determination of functionality directly on the area of interest. The technique is useful over the entire operational range of the tool temperatures. However, in this latter cases reusable test wafers are needed since lower temperatures do not fully activate the implants.

Challenges of Manufacturing Capacitor Oxide in Mixed Signal ASICS

Deposited PECVD oxides are used as the dielectric in polysilicon-polysilicon capacitors for a variety of mixed signal applications. Wafers using highly doped substrates showed good thickness uniformity. Variation across the wafer increased along with increasing substrate resistance. This variation was correlated to electrostatic charge imparted to the wafer from poorly grounded wafer handling robotics. Charging caused plasma instabilities that promoted localized adsorption and reaction of the TEOS intermediates in the initial phase of the deposition. Plasma instabilities were confirmed by measuring fluctuations in the RF power and DC bias levels.

Characterizing Dopant Contamination Using Ion Implantation

In the current work a method of investigating and characterizing dopant contamination was developed using ion implantation. An oxide integrity degradation was observed on both silicon gate oxide and poly‐poly capacitors. Boron and phosphorus contamination within or close to the surface of the respective oxides caused an elevation in premature breakdown. Using shallow implants of boron and phosphorus, the contamination effect was reproduced and characterized. Interestingly, phosphorus was most detrimental to n‐doped poly structures and boron was most detrimental to p‐doped poly structures.