Jang Hyun-Soon

Row redundancy circuit for a semiconductor memory device

Integrated circuit memory devices having reduced power consumption requirements during standby mode operation

Integrated circuit current read-amplifier design, has output voltage level control circuit provided with first and second resistors and NMOS transistor connected to their point

Frequency multiplier, data output buffer of semiconductor device, semiconductor device, and multiplication method of clock frequency

Semiconductor device with bus line loading compensation circuit

DRAM Semiconductor memory operated by external clock pulse signal

Semiconductor memory device with redundancy

An input protection device for a semiconductor integrated circuit

Frequenzmultiplizierer und zugehöriges Multiplizierverfahren sowie Datenausgabepuffer und Halbleiterbaustein

A semiconductor memory device for selecting input/output lines