Janusz Kleban

CRRD-OG: a packet dispatching algorithm with open grants for three-stage buffered clos-network switches

The clos-network architecture is well-known and widely described in the literature. It is very attractive because of its scalability. The clos-network in packet switching systems adopt the use of packet dispatching algorithms to avoid packet contention, which may occur while a packet is being routed in a switch fabric. The complexity of packet scheduling may be relaxed by providing buffers in the first and third stages in a three-stage clos network. Different dispatching schemes for buffered clos-network switches that provide 100% throughput under uniform traffic were proposed in many papers. In this paper the idea of open grants is introduced and an algorithm called concurrent round-robin dispatching with open grants (CRRD-OG) for three-stage buffered clos-network switches is proposed. This algorithm is an improved version of CRRD scheme by implementing an open grant rules and gives better performance results. The performance of CRRD-OG algorithm was evaluated and compared with results obtained for CRRD and CMSD (concurrent master-slave round-robin dispatching) schemes

Rearranging algorithms for log 2 (N, 0, p) switching networks with even number of stages

In this paper we consider the rearrangeable multi-plane banyan-type switching fabrics, called also log2(N, 0, p) switching networks, with even number of stages. For such networks different rearranging algorithms have been proposed for both: one-at-a-time and simultaneous connection models. In this paper we consider the one-at-a-time connection model, where connections arrive to the system one-by-one, and in case of blocking rearrangements are realized. To our knowledge, known algorithms require several rearrangements, and the number of such rearrangements have not been considered in the literature. We propose the new rearranging algorithm for the multi-plane banyan-type switching fabric composed of even number of stages. This algorithm leads to success using only one rearrangement. We also introduce the modified version of this new algorithm, in which rearrangement of an existing connecting path can be realized without its interruption.

The Modified MSM Clos Switching Fabric with Efficient Packet Dispatching Scheme

Next generation switches/routers will have to use switching fabrics in order to achieve the desired capacity and speed to support growing Internet traffic. For high-performance switches and routers the Clos switching fabric is very attractive because of its modular architecture and scalability. A great many packet dispatching schemes for three-stage buffered and bufferless Clos switching fabrics were proposed in the literature. Some of them provide high throughput under uniform, others under nonuniform traffic distribution. In this paper the modified MSM Clos switching fabric and a very simple packet dispatching scheme, called Static Dispatching with Rapid Unload of Buffers (SDRUB), are proposed. We show via simulation that this modified switching fabric and the described scheduling deliver very good performance in terms of throughput, cell delay and input buffers size under different traffic distribution patterns.

Packet Dispatching Algorithms with the Static Connection Patterns Scheme for Three-Stage Buffered Clos-Network Switches

Rapid expansion of the Internet and increasing demand for multimedia services fosters an immediate need for the development of new high-capacity networks capable of supporting these growing bandwidth requirements. The development of broadband transport networks resulted in the need for next generation switches/routers with high-speed interfaces and large switching capacity. The main part of every switching node is a switching fabric, which provides a connecting path between input and output lines. For high-performance switches and routers the Clos-network is very attractive because of its modular architecture and scalability. In packet switching systems packet dispatching algorithms were adopted to avoid packet contention, which may occur while a packet is being routed in a switching fabric. Different dispatching schemes for the buffered Clos-network switches were proposed in many papers. Most of them consist of request, grant and accept phases, and cannot work in the real environment. In this paper the application of static connection patterns to packet dispatching algorithms for the three-stage buffered Clos-network switches is proposed. The performance of two such algorithms, called static desynchronization (SD) and maximal matching static desynchronization (MMSD), is evaluated and compared with results obtained for CRRD (concurrent round-robin dispatching) and CMSD (concurrent master-slave round-robin dispatching) schemes. We would like to show that it is possible to use a very simple packet dispatching scheme and obtain an acceptable performance for a wide range of traffic load per input port.

Static dispatching with internal backpressure scheme for SMM Clos-network switches

Different Clos-network architectures in terms of buffer allocation were proposed in papers: SSS (Space-Space-Space), MMM (Memory-Memory-Memory), MSM (Memory-Space-Memory), and SMM (Space-Memory-Memory). The most investigated architectures are SSS and MSM. This paper deals with the packet-dispatching scheme based on static connection patterns and internal backpressure signals for the SMM Clos-network switches, where the second and third stages are made of crosspoint queued (CQ) switches. The proposed dispatching scheme is called SDIB (Static Dispatching with Internal Backpressure). Simulation results show that proposed algorithm delivers very good performance in terms of throughput, cell delay and input buffers size, under different traffic distribution patterns, for both Bernoulli and bursty traffic.

Performance evaluation of the multiple output queueing switch under different traffic patterns

Performance evaluation of the MOQ switch recently proposed by us is discussed in this paper. In the MOQ switch both the switch fabric and buffers can operate at the same speed as input and output ports. This solution does not need any speedup in the switch fabric as well as any matching algorithms between inputs and outputs. The description and the first evaluation were presented earlier. In this paper new performance measures for the proposed MOQ switch are evaluated. The simulation studies have been carried out for switches of capacity 4times4, 8times8, 16times16 and 32times32, and under different traffic patterns. The simulations results are also compared with OQ switches and VOQ switches of the same sizes and under different scheduling algorithms: iSLIP, PIM, iRRM, MMRRS, HRRM

Strict-sense nonblocking networks with k degrees of freedom

In this paper we extended the well known conditions for strict-sense nonblocking operation of the three-stage Clos switching network to the case in which k multiplexing levels (called later in this paper as k degrees of freedom) are used on input, output, and interstage links. Up till now only the cases with one multiplexing level were considered in the literature-time-division or wavelength-division. Current research shows that transmission systems with many multiplexing levels will be used in the future to increase available transmission speed in telecommunication networks. There will be also a need for switching connecting paths going through such multiplexed links in large capacity optical cross-connect systems, routers, or data center networks. In this paper we proved the strict-sense nonblocking conditions for the three-stage Clos network with k degrees of freedom. We also analyzed the cost of switching fabrics of selected capacities and with three degrees of freedom in terms of the required number of elements.

Strict-sense nonblocking networks with three multiplexing and switching levels

Changes in traffic characteristics impose new requirements on interconnection network in large data centers. These requirements force changes to be done in the network architecture and used technology. Traditional tree network topology is being replaced by Clos network, called also Leaf-Spine topology, and optical interconnection networks are added in parallel to conventional electronic switching networks. Circuit switching is also used in such network instead of packet switching. In this paper we analyze the three-stage Clos network in which three multiplexing schemes are used simultaneously on input, output, and interstage links and with circuit switching mode. Strict-sense nonblocking conditions for this network with three multiplexing levels (space, wavelength, and mode) are derived and proved. Up till now such network with at most two multiplexing levels (space and time, or space and wavelength) has been considered.

Performance Evaluation of Selected Packet Dispatching Schemes for the CBC Switches

The CBC stands for the Central-stage Buffered Clos-network. This kind of switching fabric was proposed and theoretically evaluated by F. Wang and M. Hamdi. In this paper new packet dispatching schemes for the CBC switches are proposed and evaluated. We study three such schemes, called RGNA (Request -- Grant with No Association), RGAM (Request - Grant with Associated output Modules), and RGAP (Request - Grant with Associated output Ports). Our research is aimed at finding an answer to the question: what kind of packet dispatching scheme should be used in the CBC switch to achieve very good performance in terms of throughput, cell delay and central buffers size. The uniform and nonuniform traffic distribution patterns are used to evaluate the performance of the CBC switch. Using computer simulation we try to fill an important gap between the theory and practical implementation of interesting switch architecture.

Novel Switch Architectures

In this paper we discussed different switch architectures. We focus mainly on optical buffering. We investigate an all-optical buffer architecture comprising of cascaded stages of quantum-dot semiconductor optical amplifier- based tunable wavelength converters, at 160 Gb/s. We also propose the optical buffer with multi-wavelength converters based on quantum-dot semiconductor optical amplifiers. We present multistage switching fabrics with optical buffers, where optical buffers are based on fibre delay lines and are located in the first stage. Finally, we describe a photonic asynchronous packet switch and show that the employment of a few optical buffer stages to complement the electronic ones significantly improves the switch performance. We also propose two asynchronous optical packet switching node architectures, where an efficient contention resolution is based on controllable optical buffers and tunable wavelength converters TWCs.