Janusz Sosnowski

Transient fault tolerance in digital systems

It is hard to shield systems effectively from transient faults (fault avoidance techniques). So some other means must be employed to assure appropriate levels of transient fault tolerance (insensitivity to transient faults). They are based on fault-masking and fault recovery ideas. Having analyzed this problem, the author identifies critical design points and outlines some practical solutions that refer to efficient on-line detectors (detecting errors during the system operation) and error handling procedures. This framework provides a basis for understanding transient fault problems in digital systems. It can be helpful in selecting optimum techniques to mask or eliminate transient fault effects in developed systems.<<ETX>>

Detection of control flow errors using signature and checking instructions

An approach is presented to the online detection of control flow errors caused by transient and intermittent faults in microprocessor systems. It is based on the idea of signatured instruction streams. Signatures are embedded into the program memory using the monitored processor instructions. Compared with existing techniques, the presented approach is universal and can be easily implemented using off-the-shelf programmable array logic and LCA circuits. The hardware overhead ranges from one to several chips for microprocessors with 8-bit and 16-bit data buses. Program memory overhead is 10-20% and quite often no extra memory chip is required. A special software module has been developed to embed signatures and checkpoints into application programs.<<ETX>>

Safety issues in avionics and automotive databuses

Abstract In avionics and automotive applications of computing, special care must be taken of issues related to safety. Assurance must be provided that computer hardware or software does not contribute to situations, which may cause loss of life or significant property damage. One aspect of this concern is the design of databuses, which provide a medium to exchange information among various electronics devices in a vehicle. Unfortunately, only a few aspects of bus design have been sufficiently covered in the research studying system safety. This paper reviews and compares available information on bus specifications. Databuses are discussed regarding their properties, such as signal characteristics and bus protocols, with respect to safety.

Software-based self-testing of microprocessors

Hardware-based self-testing techniques have limitations in the performance and area overhead. Those can be eliminated using software-based self-testing. In this paper, we investigate capabilities of the microprocessor testing by software procedures taking into account system environment constraints. Special attention is paid to microarchitectural features of pipelined and superscalar processors. New test strategies are proposed combining deterministic and pseudo-random approaches supported by the available hardware mechanisms (test registers, on-chip monitoring circuitry, etc.), which improve testability features. The test effectiveness is studied using various test coverage measures (stimuli, circuit stressing), statistical and fault injection tools. To demonstrate the utility of the proposed methodology, it has been applied to commercial microprocessors and experimental results are presented in this paper.

In-system testing of cache memories

Caches embedded in microprocessor systems are implemented with limited observability and controllability. Hence they create many problems in testing. This paper gives a methodology of developing user test programs for data and instruction caches with various organization.

Software Implemented Fault Inserters

Abstract The paper deals with the problem of checking system fault susceptibility in simulation experiments. Three fault simulators are presented. They are based on the idea of disturbing system states (registers, memory locations). Two systems deal with Win 32 environment and one with Linux. They differ in implementation and functional capabilities. The use of fault injection in system dependability evaluation is illustrated in a sample of experiments.

Analyzing Fault Susceptibility of ABS Microcontroller

In real-time safety-critical systems, it is important to predict the impact of faults on their operation. For this purpose we have developed a test bed based on software implemented fault injection (SWIFI). Faults are simulated by disturbing the states of registers and memory cells. Analyzing reactive and embedded systems with SWIFI tools is a new challenge related to the simulation of an external environment for the system, designing test scenarios and result qualification. The paper presents our original approach to these problems verified for an ABS microcontroller. We show fault susceptibility of the ABS microcontroller and outline software techniques to increase fault robustness.

Analyzing the effectiveness of fault hardening procedures

The paper addresses the problem of evaluating the effectiveness of fault hardening procedures based on software redundancy. We analyze the time and memory overhead of fine-grained and coarse-grained error detection and correction techniques. We check the impact of the involved overhead on fault coverage. The presented considerations are illustrated with fault injection experimental results.

Developing Fault Injection Environment for Complex Experiments

The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.

Software Implementation of Explicit DMC Algorithm with Improved Dependability

The paper presents an approach to improve the dependability of software implementation of the explicit DMC (Dynamic Matrix Control) Model Predictive Control (MPC) algorithm. The investigated DMC algorithm is implemented for a control system of a rectification column - a process with strong cross-couplings and significant time delays. The control plant has two manipulated inputs and two outputs. The fault sensitivity of the proposed implementation is verified in experiments with a software implemented fault injector. The experimental results prove the efficiency of proposed software improvements.