Jason Cantone

Towards electrical testable SOI devices using Directed Self-Assembly for fin formation

The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Towards manufacturing of advanced logic devices by double-patterning

As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

Utilization of spin-on and reactive ion etch critical dimension shrink with double patterning for 32 nm and beyond contact level interconnects

Spin-on chemical shrink, reactive ion etch [RIE] shrink and litho-etch-litho-etch [LELE] double patterning have been utilized to produce dense 90 nm pitch, 26 nm bottom CD contacts starting from 65 nm CD, 126 nm diagonal pitch as printed features. Demonstrated lithographic process window, post etch pattern fidelity, CD, and CD uniformity are all suitable to production. In addition, electrical test results shows a comparable defect a ratio vs. a no chemical shrink baseline.

Assessment of negative tone development challenges

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

Engine for characterization of defects, overlay, and critical dimension control for double exposure processes for advanced logic nodes

As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for our DETO process.

Defectivity issues in topcoatless photoresists

One method currently being employed to reduce the overall lithography process complexity and cost is the utilization of a topcoatless photoresist. The development of these materials administers an additive to create the same hydrophobic characteristics as those created by advanced topcoats. The main challenge for topcoatless resists is to increase the hydrophobicity without causing too much inhibition at the resist surface which leads to bridging or residue-type defects. The key to such a design lies in creating a balance between leaching control and dissolution characteristics of the resist without degrading lithography performance and increasing defectivity. The addition of these hydrophobic additives into existing ArF photoresist systems has been shown to increase both receding contact angle and advancing contact angle in water-based immersion lithography. In this work, the authors have demonstrated that the defectivity levels of topcoatless resist are equal to or better than the industry standard of t...

Negative-tone imaging (NTI) at the 22nm node: process and material development

With 22nm logic node arriving prior to EUV implementation, alternative immersion optical lithographic processes are required to drive down to smaller feature sizes. There is an ongoing effort to examine the application of the negative tone imaging (NTI) process for current and future nodes. Although NTI has previously shown difficulties with respect to swelling, high chemical reactivity with oxygen, and the need for special equipment needed for the solvent-based development, NTI photoresists (PR) typically exhibit stronger adhesion to silicon than that of positive tone photoresists (a characteristic that helps mitigate pattern collapse). We will provide suggestions on how to improve the image quality, as well as the resulting defectivity, for desired geometries. This paper will primarily focus on the full litho process optimization and demonstrate repeatable, and manufacturable critical dimension uniformity (CDU), and defectivity optimization for trench and via structures.

In-line E-beam metrology and defect inspection: industry reflections, hybrid E-beam opportunities, recommendations and predictions

At SPIE 2013 in Metrology, Inspection, and Process Control for Microlithography an invited paper was published titled “In-line E-beam wafer metrology and defect inspection: the end of an era for image-based critical dimensional metrology? New life for defect inspection”. Three years have passed and numerous developments have occurred as predicted in this paper. The development of E-beam tools that can concurrently handle metrology and defect applications is one of the primary developments. In this paper, the capabilities of these new E-beam tools and their current use cases will be discussed in the areas of Critical Dimension Uniformity (CDU), In-die overlay, Hot spot and Physical defect inspection. Emphasis will be placed on use cases where “massive” CDU data is collected in order to increase yield learning for manufacturing (14nm) and decrease cycles of learning for development (7nm). Additionally, some of the other subject material from the previous publication will also be discussed such as the current state of E-beam critical dimension image fidelity and physical defect detection capabilities. Lastly, future directions and opportunities for In-line E-beam including Multi-beam and/or Multi-column E-beam will be discussed.

EUV and optical lithographic pattern shift at the 5nm node

At the 5 nm technology node there are competing strategies for patterning: high-NA EUV, double patterning 0.33 NA EUV and a combination of optical self-aligned solutions with EUV. This paper investigates the impact of pattern shift based on the selected patterning strategy. A logic standard cell connection between TS and M0 is simulated to determine the impact of lithographic pattern shift on the overlay budget. At 5 nm node dimensions, high-NA EUV is necessary to expose the most critical layers with a single lithography exposure. The impact of high-NA EUV lithography is illustrated by comparing the pattern shift resulting from 0.33 NA vs. 0.5x NA. For the example 5 nm transistor, cost-beneficial lithography layers are patterned with EUV and the other layers are patterned optically. Both EUV and optical lithography simulations are performed to determine the maximum net pattern shift. Here, lithographic pattern shift is quantified in terms of through-focus error as well as pattern-placement error. The overlay error associated with a hybrid optical/self-aligned and EUV cut patterning scheme is compared with the results of an all EUV solution, providing an assessment of two potential patterning solutions and their impact the overall overlay budget.