Jason M. Agron

Automating the design of mLUT MPSoPC FPGAs in the cloud

Modern platform FPGAs are over the million-LUT level, large enough to support complete heterogeneous Multiprocessor System-On-Chips (MPSoCs). Constructing systems with 10s of processors is currently feasible using existing manual methods within vendor-specific CAD tools. However these manual, by-hand, approaches will not be feasible for constructing future systems with 100s to 1,000s of processors. Instead, new automated system assembly approaches will be required to handle these levels of system complexity and diversity. In this paper we present a new automated design flow for creating such next generation heterogeneous MPSoCs. An integral part of the MPSoPC system created is the inclusion of a general purpose PThreads-compliant HW/SW co-designed operating system and heterogeneous compiler. Our design flow has been placed in the cloud and is freely accessible across the Internet.

Operating System Structures for Multiprocessor Systems on Programmable Chip

Chips are moving from single-core systems to much more complex, heterogeneous many core systems. While heterogeneous architectures promise high performance, they are also challenging our ability to port our existing operating systems to abstract the heterogeneous components into a unified architecture. Baseline solutions to resolve heterogeneity issues within many cores use Remote Procedure Calls (RPC) for applications running on slave processors to access a traditional monolithic kernel running on a common master node. Micro kernels are once again re-emerging to eliminate the central bottleneck of the monolithic kernel. In both cases the RPC methods used for communications increase the overhead of system services, counter to the desire of breaking threads up into finer grained services to match and scale with increasing numbers of processors. In this paper we show how new invocation mechanisms built as hardware primitives in combination with new a new hw/sw co-designed micro kernel can resolve heterogeneity issues in a framework that supports the level of scalability required for next generation systems. We present experimental results as well as a new queuing model to show how both monolithic and micro kernels that rely historical interrupt mechanisms cannot support scalability beyond small numbers of processors. We also show through these results the potential scalability of a hardware kernel based micro kernel with new lightweight invocation mechanisms.