Javier Martinez

Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm

This paper shows that partial reconfiguration can notably improve the area and throughput of symmetric cryptographic algorithms implemented in FPGAs. In most applications the keys are fixed during a cipher session, so that several blocks, like module adders or multipliers, can be substituted for their constant-operand equivalents. These counterparts not only are faster, but also use significantly less resources. In this approach, the changes in the key are performed through a partial reconfiguration that modifies the constants. The International Data Encryption Algorithm (IDEA) has been selected as a case-study, and JBits has been chosen as the tool for performing the partial reconfiguration. The implementation occupies an 87% of a Virtex XCV600 and achieves a throughput of 8.3 GBits/sec.

A remote laboratory for debugging FPGA-based microprocessor prototypes

In this paper, a framework for testing microprocessor prototypes is presented. A RISC microprocessor is designed by students using VHDL language and adapted to be implemented on a FPGA device. The correct behaviour of the designed microprocessor is checked executing test programs written and compiled by the students for this microprocessor. Using a Web client, users send test programs and a file with the design to a remote laboratory where it is loaded on a real FPGA device. A set of tools for debugging the remote execution of the tests has been developed, using a graphical interface similar to other debugging tools. Groups of selected students of a computer architecture course have participated in this experience. The good opinions received from the students, suggest the incorporation of this remote laboratory experience in the next regular course.

An efficient and expandable hardware implementation of multilayer cellular neural networks

Abstract This paper proposes a new CNN architecture conceived for hardware implementation of complex ML-CNNs on programmable devices. The architecture is completely modular and expandable, and includes advanced features such as non-linear templates, time-variant coefficients or multi-layer structure. We also present an implementation platform based on the pre-designed but user-configurable FPGA processing modules that inherit the modularity and expandability of the logical architecture. All the modules share the same, properly designed, I/O interface, so the platform can be configured to accommodate CNNs of any size or structure, composed of a number of processing blocks that can be physically distributed over several FPGA boards. Our Carthagonova architecture makes use of a temporal processing approach with a super-pipelined unfolded cell structure, leading to the maximum degree of parallelism while still keeping the most efficient use of FPGA resources. Both the CNN architecture and the hardware platform have been validated by the implementation of a real-time video processing system, showing that they conform a valuable set of tools for the development of CNN-based applications.

Real measures, virtual instruments

This paper presents the realisation of a remote lab on a European scale. The involved countries are France, Germany, and Spain. The architecture of the lab is described and the functionality has been tested. It concerns the instrumentation in the field of microelectronics. It has been applied to the characterisation of MOS transistors.

New emulated discrete model of CNN architecture for FPGA and DSP applications

A new approach to Cellular Neural Networks discrete model is proposed. This approach is focused on CNN implementation on reconfigurable hardware architectures and DSP microprocessors. CNN are analysed from the perspective of Systems Theory, giving rise to an alternative model to those found in the literature available. Dynamic equations and their solutions, stability analysis and real-time implementation architecture are described in this paper as the most relevant points in the development of our model. The main results, obtained from different simulations, evidence the usefulness and functionality of the model.

Implementation of a discrete cellular neuron model (DT-CNN) architecture on FPGA

This paper explores different alternatives to carry out a model of digital CNN from the point of view of its implementation on FPGAs. It shows the developments of four different DT-CNN models obtained from different transformations made to the original continuous model of CNN. Next, each discrete approach is simulated and compared with the rest of approaches and the continuous models. The objective of this study is to find the approach which best emulates the continuous neuron model at minimum computational cost. The simulations and temporal analysis of the discrete models have been made both in feedback and open system in order to verify their functionality. Finally, the architecture of the best model is implementated on an FPGA obtaining very interesting results.

Interact-DDM: a solution for the integration of domestic devices on network management platforms

The paper presents Interact-DDM (interact - domestic device management), a solution that integrates domestic devices with traditional computer networks. The architecture proposal is based on TCP/IP network management standards: SNMP protocol and management information bases (MIB). The centralized management operation has been enhanced with additional capabilities integrated on the agents. The design has been performed permitting a very flexible device definition and dynamic configuration. This is achieved by the meta-definition of devices in the system MIB. A laboratory experiment has been deployed to check and validate the design proposed, where multiple configurations have been tested, and the design modularity has been proved.

Study of the contrast processing in the early visual system using a neuromorphic retinal architecture

In this paper we propose a retinal architecture that incorporates the neural circuits found in the different retinal regions. It is implemented in a reconfigurable system for observing in real time the contrast processing capabilities of each retinal region over the provided stimuli. The retina model is based on a discrete-time cellular neural network (DTCNN) that will be implemented on reconfigurable architecture (FPGA) with a time multiplexing approach. This architecture is able to incorporate 50 million neurons in its structure for processing video in real time. It has been observed that the contrast detection and the detail resolution are influenced by the convergence factor of neurons and by the lateral inhibition, specific characteristics of each neural circuit.

Skin Color Detection for Real Time Mobile Applications

In the last decade, skin color has proven to be a useful cue for recognition and tracking of face and hand, and skin color segmentation has become the first step in several processing tasks. With the aim of overcoming the weak points that existing software solutions show in real time mobile applications, we propose an FPGA-based implementation of a skin classifier. The skin classification algorithm and its hardware architecture are herein described. Results in terms of classification performance, processing rate and hardware resources used are presented.

Implementation of a CNN-based retinomorphic model on a high performance reconfigurable computer

The complexity of hardware design methodologies represents a significant difficulty for non-hardware focused scientists working on accelerating the simulation of complex bio-inspired applications. An emerging generation of electronic system level (ESL) design tools is been developed, which allow software-hardware codesign and partitioning of complex algorithms from high level language (HLL) descriptions. These tools, together with high performance reconfigurable computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of highly parallelizable algorithms. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, are analyzed. A model for the first synapse of the retina, based on a discrete-time sequential CNN architecture suitable for FPGA implementation proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results showed that, with a minimum development time, a 10xacceleration, when compared to the software emulation, can be obtained.