Jayanta Bhadra

A Survey of Hybrid Techniques for Functional Verification

This article surveys recent advances in hybrid approaches for functional verification. These approaches combine multiple verification techniques so that they complement one another, resulting in superior verification effectiveness.

On soft error rate analysis of scaled CMOS designs: a statistical perspective

This paper re-examines the soft error effect caused by cosmic radiation in sub 90nm technologies. Considering the impact of process variation, a number of statistical natures of transient faults are found more sophisticated than their static ones. We apply the state-of-the-art statistical learning algorithm to tackle the complexity of these natures and build compact yet accurate generation and propagation models for transient fault distributions. A statistical analysis framework for soft error rate (SER) is also proposed on the basis of these models. Experimental results show that the proposed framework can obtain improved SER estimation compared to the static approaches.

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

Sequential Automatic Test Pattern Generation is extremely computation intensive and produces acceptable results only on relatively small designs. Hierarchical approaches that target one module at a time and use ad-hoc abstractions for the rest of the design, have shown promising results in reducing the test generation complexity. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical test generation. The technique to systematically obtain a “constraint slice” for each embedded module under test within a design, is described in detail. The technique has been incorporated in an automated tool for Verilog designs, and results on large benchmark circuits show the significant benefits of the approach.

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, architectural test generation techniques have limitations in terms of exercising intricate micro-architectural artifacts. Therefore, it is necessary to use micro-architectural details during test generation. Furthermore, there is a lack of automated techniques for directed test generation targeting micro-architectural faults. To address these challenges, we present a directed test generation technique at micro-architectural level for functional validation of microprocessors. A processor model is described in a temporal specification language at micro-architecture level. The desired behaviors of micro-architecture mechanisms are expressed as temporal logic properties. We use decompositional model checking for systematic test generation. Our experiments using a processor based on the power architecture technology shows very promising results in terms of test generation time as well as test program length.

Novel test detection to improve simulation efficiency: a commercial experiment

Novel test detection is an approach to improve simulation efficiency by selecting novel tests before their application [1]. Techniques have been proposed to apply the approach in the context of processor verification [2]. This work reports our experience in applying the approach to verifying a commercial processor. Our objectives are threefold: to implement the approach in a practical setting, to assess its effectiveness and to understand its challenges in practical application. The experiments are conducted based on a simulation environment for verifying a commercial dual-thread low-power processor core. By focusing on the complex fixed-point unit, the results show up to 96% saving in simulation time. The main limitation of the implementation is discussed based on the load-store unit with initial promising results to show how to overcome the limitation.

Enhancing signal controllability in functional test-benches through automatic constraint extraction

Functional test-bench development is a tedious and time-consuming process that requires tremendous engineering effort. Developing proper test-benches is crucial for both functional verification and post-silicon performance validation. Constrained random test generation is a popular approach to alleviate the burden of test-bench development. This paper presents an automatic constraint extraction tool that can be easily integrated with an existing commercial constrained random test generation framework. This tool extracts constraints by analyzing test-bench simulation data. These constraints, when added into a test-bench, can provide controllability of signals that are deeply embedded in a complex design. We develop simulation data mining algorithms for constraint extraction and demonstrate the effectiveness of our approach based on OpenSparc Tl microprocessor.

An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology

Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named σ-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that σ-Iddq testing achieves a higher classification accuracy in a 45 nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently.

A formal framework for verification of embedded custom memories of the Motorola MPC7450 microprocessor

In this presentation, we will deal with verification of custom designed embedded memories. Using our paradigm, one can abstract the behavior of a memory block by a couple of artifacts—one representing its contents, and another representing its interface. We make use of the well known behavioral model known as the Efficient Memory Model (EMM) [29, 30] to represent contents of memories. We provide a methodology using which the behavior of a switch (or equivalently, transistor) level device can be specified using parameterized regular expressions. These entities can be used to abstractly describe the behavior of a bunch of switches that represent the interface of a memory. An automaton that we construct out of an abstract memory interface definition represents an abstraction of the memory interface itself. We show that such an automaton also forms a transducer that is a simulation model in a symbolic simulation environment. An EMM representing a memory core in conjunction with a transducer representing its interface is used as an abstraction of a complete memory during our automatic verification process.We also present a language formalism using which we show that the outputs from the transducers that are generated from the abstract specifications are weaker than or equal to the outputs defined by the regular expressions, in a partially ordered output space. We show that although the regular expressions are defined over exact and legal input strings, the transducers computed from them can provide outputs even when provided with weak or illegal input strings. This is an absolute necessity in order to have the capability to produce outputs when treated as a reactive system embedded in a symbolic simulation environment. Thus, we show that the simulation model generated by our technique is an conservative approximation of the corresponding abstract specification.We present a simple theory of composition that can be used to compose different simulation models used in our technique. Memories consisting of several ports result into several user-provided abstract specifications, which in turn result into several transducers that can be composed into a single transducer. That transducer in turn can be composed to a simulation model of an EMM. Our simple theory of composition also enables one to compose the abstract state space a memory core along with its ports with the concrete state space of the circuitry surrounding the memory core. We have shown that the composite simulation model representing the complete circuit has a partially ordered state space that (a) forms a complete lattice, and (b) that has a monotonic state transition function, that makes it suitable for being used in a symbolic simulation environment making use of Symbolic Trajectory Evaluation (STE) [27].The verification paradigm used is STE. For Motorola high performance microprocessors, switch level models are hand designed assuming that corresponding RTLs are golden models. Therefore, checking of equivalence between the two models is of absolute necessity as the RTL needs to be predictive of silicon behavior. We have developed a tool based on the proposed technique and used it to check that RTL descriptions of custom memories have been correctly implemented by transistor level descriptions of the same, augmented with abstract specifications of their cores. Our example circuits were taken from the state of the art Motorola MPC7450 microprocessor, a Motorola PowerPC. Experimental evidence testify to the effectiveness of the technique in catching subtle bugs in data path circuitry.

Automatic generation of design constraints in verifying high performance embedded dynamic circuits

Design constraints are artifacts that model an environment of a design under verification by restricting input stimuli to plausible valuations. Judicious usage of design constraints can be effective in eliminating false verification results. Given a particular verification problem, however, it is a difficult proposition to write down all the necessary constraints. We present a technique for automatic generation of design constraints from simple user-provided information about potential design environments. Our method generates a set of design constraints representing varying degrees of assumptions about potential environments of a dynamic circuit. We also present experimental results on verification of custom designed embedded dynamic circuits taken from the Motorola MPC7455 microprocessor.

Automatic validation test generation using extracted control models

We present a procedure for the automatic generation of tests covering control states of a sequential circuit. The procedure consists of extracting a control model of the circuit under test and then using this model to guide the search for concrete executions or witnesses. We present results of experiments using the procedure on a communication chip from industry as well as an implementation of the ARM 2 processor.