Jayasree Dattagupta

O(n) routing in rearrangeable networks

Abstract In (2n−1)-stage rearrangeable networks, the routing time for any arbitrary permutation is Ω(n2) compared to its propagation delay O(n) only. Here, we attempt to identify the sets of permutations, which are routable in O(n) time in these networks. We define four classes of self-routable permutations for Benes network. An O(n) algorithm is presented here, that identifies if any permutation P belongs to one of the proposed self-routable classes, and if yes, it also generates the necessary control vectors for routing P. Therefore, the identification, as well as the switch setting, both problems are resolved in O(n) time by this algorithm. It covers all the permutations that are self-routable by anyone of the proposed techniques. Some interesting relationships are also explored among these four classes of permutations, by applying the concept of ‘group-transformations’ [N. Das, B.B. Bhattacharya, J. Dattagupta, Hierarchical classification of permutation classes in multistage interconnection networks, IEEE Trans. Comput. (1993) 665–677] on these permutations. The concepts developed here for Benes network, can easily be extended to a class of (2n−1)-stage networks, which are topologically equivalent to Benes network. As a result, the set of permutations routable in a (2n−1)-stage rearrangeable network, in a time comparable to its propagation delay has been extended to a large extent.

Isomorphism of conflict graphs in multistage interconnection networks and its application to optimal routing

A study on the isomorphism of conflict graphs in multistage interconnection networks (MINs) and its applications is outlined. A concept called group-transformation is introduced for the baseline network, which induces an equivalence partition on the set of all permutations. All members belonging to the same equivalence class have isomorphic conflict graphs. Thus, determination of conflict resolution of one permutation results in determination of conflict resolution of all other equivalent members. The BPCL (bit-permute-closure) class of permutations is defined, for which the conflict resolution problem can be settled in linear time by an earlier algorithm developed only for the BPC (bit-permute-complement) permutations. It is proved that for an N*N MIN, mod BPCL mod >or=n 2N-1, in contrast to mod BPC mod n 2n, (nlog/sup 2/ N). Conflict graphs for BPCL permutations are also characterized. An O(N) time algorithm to check membership of a given permutation to the BPCL class is described. All of these results are generalized to extend their applicability to other unique-path full-access MINs. >

Hierarchical classification of permutation classes in multistage interconnection networks

This paper explores a new hierarchy among different permutation classes, that has many applications in multistage interconnection networks. The well-known LC (linear-complement) class is shown to be merely a subset of the closure set of the BP (bit-permute) class, known as the BPCL (bit-permute-closure) class; the closure is obtained by applying certain group-transformation rules on the BP-permutations. It indicates that for every permutation P of the LC class, there exists a permutation PI in the BP class, such that the conflict graphs of P and P* are isomorphic, for n-stage MINs. This obviates the practice of treating the LC class as a special case; the existing algorithm for optimal routing of BPC class in an n-stage MIN can take care of optimal routing of the LC class as well. Finally, the relationships of BPCL with other classes of permutations, e.g., LIE (linear-input-equivalence), BPIE (bit-permute-input-equivalence), BPOE (bit-permute-output-equivalence) are also exposed. Apart from lending better understanding and an integral view of the universe of permutations, these results are found to be useful in accelerating routability in n-stage MINs as well as in (2n-1)-stage Benes and shuffle-exchange networks. >

Analysis of conflict graphs in multistage interconnection networks

For multistage interconnection networks (MINs), the authors introduce a concept called group transformation that partitions the set of all permutations into several equivalence classes, such that all members belonging to the same class have isomorphic conflict graphs. The authors then define the BPCL (bit-permute-closure) class of permutations and show that the conflict resolution problem can be settled in linear time for BPCL by an earlier algorithm developed by Raghavendra and Varma (see IEEE Trans.Comput., vol. C-35, no.4, 1986) for BPC (bit-permute-complement) permutations only. The ability to apply Raghavendras algorithm is enhanced to a great extent. The authors also describe an O(N/sup 2/) algorithm to decide whether or not a given permutation P belongs to the BPCL class.<<ETX>>

Two-Pass Rearrangeability in Faulty Benes Networks

Existing fault-tolerant routing schemes for Benes networks either consider only the control line stuck-at faults, or handle the switch faults by some graceful degradation routing schemes that reconfigure the network into a smaller system with minimal loss. Now, even in the presence of a single switch fault in anN×NBenes networkB(n), (n= log2N), noN×Npermutation can be realized in a single pass. In this paper, we attempt to characterize the switch fault sets inB(n), in the presence of which the network is always capable of realizing any arbitraryN×NpermutationPin two passes, such that any source?destination path is set up in a single pass, no recirculation is needed, but the whole set ofNsource?destination paths ofPis partitioned in two subsets and are realized in two successive passes. We propose an algorithm that will detect if the switch fault set present in aB(n), belongs to this class; if it is yes, we present another algorithm that computes the fault-tolerant routing to realize any arbitrary permutationPin two passes. This scheme enables us to makeB(n) fault-tolerant in the presence of a restricted class of multiple switch faults, without any recirculation through intermediate nodes, or any reconfiguration of the system.

Improvement in the speed of FFT processors using segmented memory and parallel arithmetic units

Abstract In this paper, an organization of FFT processor has been described using the idea of memory segmentation and interstage shuffling which results in a reduction of memory read/write time by 50 percent. Two schemes have been presented, one using only one arithmetic unit and the other with two arithmetic units.

Distributed Algorithm for Power Aware Connected Dominating Set for EfCcient Routing in Mobile Ad Hoc Networks

Efficient routing in ad hoc mobile environment with an economic use of battery power is an important problem and conventional routing protocols are unsuitable there due to static choice of routing paths without consideration of remaining battery power of the nodes. In this paper, we propose a simple and efficient distributed algorithm for calculating power aware connected dominating set for Ad hoc wireless networks. To enhance the lifetime of each node, which will in turn enhance the lifetime of the network, energy consumption here is balanced among different nodes of the network. Nodes are alternated in being selected to become a member of connected dominating set, which would enhance the lifetime of the network. In our approach each node select another node as its dominating neighbor depending on the status vector of its neighbor set. The status of a node is calculated based on its node degree and remaining battery power. The algorithm has 0(Δ2) time complexity and O(m) message complexity, where Δ is the maximum node degree and m is the number of edges in the topology graph. The dominating sets we obtain are in general comparable in size to that obtained in [1]. We ensured mobility support in our algorithm and our simulation result shows that, under the condition of mobility better lifespan is obtained using our approach as compared to other power aware approach.

On synthesizing cube and tree for parallel processing

Abstract In this paper we propose a VLSI implementable architecture called Cube Connected Tree having advantageous properties of both tree and hypercube. This structure has a fixed low degree of nodes for any size of the network unlike the hypercube where the node degree is dependent on the size of the hypercube. The degree-diameter product metric [26]of CCT is low compared to that of a hypercube of comparable size. It overcomes the data congestion problem near the root of the binary tree by having multiple roots in the structure, thereby enhancing the I/O bandwidth of the system. The complexity of the VLSI layout of this structure has been addressed within the grid model of Thompson [12]. By using spare links and PEs, fault tolerance capabilities of the system have been enhanced. Easy programmability of this structure has been demonstrated by designing polylogarithmic algorithms for sorting and discrete Fourier transform.

Ring-connected trees: a multipurpose VLSI architecture for parallel processing

Abstract In this paper we propose a new general purpose VLSI architecture called ring-connected trees (RCT) for parallel processing. RCT requires less hardware in terms of processing elements and connecting links compared to a mesh-of-tree of comparable size and its diameter is less than that of mesh. It requires less chip area, less maximum edge length and crossing number compared to those required by mesh-of-tree [1] [F.T. Leighton, Layout for the shuffle-exchange graph and lower bound techniques for VLSI, Ph.D. dissertation, Department of Mathematics, MIT 1981] under the Grid model of Thompson [2] [C.D. Thompson, Area-time complexity for VLSI. Technical report, Division of Computer Science, University of California, Berkeley, CA, January 1984]. By using spare PEs and links, RCT is made to tolerate multiple faults. Suitability of this architecture for multipurpose applications is demonstrated by designing parallel version of algorithms for a number of common computational problems. This structure requires linear and sublinear time for these algorithms and this is quite reasonable considering the simpler nature of the architecture.

Fault identification and routing in Benes networks

Abstract An N × N Benes network B ( n ) ( n = log 2 N ), being a rearrangeable network, can realize any N × N permutation in a single pass. But even in the presence of a single switch fault in B ( n ), two passes are necessary to realize any N × N permutation. In this paper, we attempt to characterize the switch fault sets in B ( n ), in the presence of which the network is always capable of realizing any arbitrary N × N permutation P in two passes, such that every source-destination connection is set up in a single pass, i.e., no recirculation is needed, but the whole set of N source-destination connections of P is partitioned in two subsets and are realized in two successive passes. An algorithm has been developed to test if the faulty B ( n ) is capable of realizing any arbitrary permutation in two passes by our technique; if it is yes, another algorithm also has been presented that computes the fault-tolerant routing to realize any arbitrary permutation P in two passes, through the faulty B ( n ). Finally, for this routing technique, the exact locations of the faults are not important, only the information of some optimal regions around the fault is sufficient. This feature actually enables us to develop very fast and simple procedures for identification of faulty regions of B ( n ), in the presence of multiple switch faults. Therefore, this fault-tolerant routing scheme enables us to make B ( n ) fault-tolerant in the presence of an easily-testable class of multiple switch faults, without any recirculation through intermediate nodes, or any reconfiguration of the system.