Je-Kuan Jau

S-parameter formulation of quality factor for a spiral inductor in generalized two-port configuration

This paper formulates various quality (Q) factors associated with the applications of on-chip spiral inductors to radio-frequency integrated circuits using S-parameters. The formulations start with the Q factor of a spiral inductor in a generalized two-port configuration based on a new complex-power approach and then extend to the Q factors of a tank and matching circuits that use the spiral inductors. In the demonstration, the two-port S-parameters for a series of CMOS spiral inductors have been measured to further generate such various Q factors for a many-sided evaluation of the inductor performance.

Synthesis of a super broadband model for on-chip spiral inductors

A modified T-section equivalent circuit is proposed to model on-chip spiral inductors with extremely large bandwidth. This developed model combines a five-element modified T-section to include up to half-wavelength long transmission-line effects, and parallel and series feedback resonators to account for higher-order resonances present in the coil-coupling and ground-return paths. The modeled S parameters show excellent agreement with measured results over the entire measurement frequency range of 20 GHz and 50 GHz for a series of planar spiral inductors implemented on silicon and InGaAs substrates, respectively. The effective modeling bandwidth is at least several times larger than in a conventional PI-section model.

Highly Efficient Multimode RF Transmitter Using the Hybrid Quadrature Polar Modulation Scheme

This research first presents a hybrid quadrature polar modulator to drive the power amplifier (PA) highly efficiently in a wireless RF transmitter required for multi-mode operation. The proposed modulator consists of a quadrature modulator for processing the RF modulated carrier and a class-S modulator for processing the envelope signal. Since both quadrature and class-S modulators deliver signals with envelope variation, the double amplitude modulation distorts the RF modulated signal at the PA output. Therefore, a digital predistorter is required in front of the hybrid quadrature polar modulator for compensation. The use of such predistorted drive signals can help reducing the average DC and input RF drive powers and the output feed-through levels so as to enhance the power added efficiency and adjacent channel power rejection remarkably

A novel EER transmitter using two-point delta-sigma modulation scheme for WLAN and 3G applications

A novel transmitter architecture is proposed for wireless local area networks (WLAN) and 3/sup rd/ generation (3G) mobile applications. The transmitter is based on the envelope elimination and restoration (EER) architecture applied with two-point delta-sigma modulator (TPDSM). It can integrate digital modulators and power amplifiers without mixers effectively. In addition, the power amplifier can deal with non-constant envelope modulations like QPSK highly efficiently.

Envelope Following-Based RF Transmitters Using Switching-Mode Power Amplifiers

This research presents a high-efficiency linear radio frequency transmitter applying the envelope-following technique to a switching-mode power amplifier. The use of predistorted envelope and quadrature-modulated signals can linearize the nonlinear behavior with fairly high average efficiency. The experimental results show that the proposed transmitter can deliver a 1.9-GHz CDMA2000 1times signal with high adjacent channel power ratio, low error vector magnitude, and high power added efficiency over a wide range of modulated output power

Highly linear upconverter MMIC designs with complete package and test board effects for CDMA applications

1.9 GHz upconverter MMICs are designed and implemented using GaAs HBT foundry process. A crucial goal for the design is to achieve the high linearity required in CDMA systems with low idle currents. In addition, complete package and test board effects need to be considered rigorously. The proposed design adopts a class-AB input stage in a Gilbert cell to enhance the linearity. Another design based on the conventional emitter degeneration technique is also implemented on the same chip for comparison. The chip is finally housed in a 24-pin bump-chip carrier (BCC) package and surface-mounted on a test board. Both RF and LO ports are internally matched to 50 /spl Omega/ on chip. A single supply voltage of 3V is used. The measured results show that with a reference input power of -10 dBm for IS-95 CDMA applications, the class-AB design achieves an adjacent channel power ratio (ACPR) of -44.9 dBc with a consumed current of 15 mA, while the emitter degeneration design achieves an ACPR of -43.8 dBc with a consumed current of 28.5 mA.. Package and test board effects are analyzed using the 3-D EM simulation tool and transformed into the equivalent-circuit elements. The simulation including package and test board effects can predict the measured results quite well.

Linear interpolation scheme for compensation of path delay difference in an envelope elimination and restoration transmitter

The linearity of an envelope elimination and restoration (EER) transmitter depends primarily upon the bandwidth of the baseband envelope amplifier and path delay difference between the envelope and phase signals. A method for compensating the path-delay difference based on the baseband DSP technique has been proposed in this paper. This technique uses a baseband interpolation process to reduce the intermodulation effects of an EER transmitter. The improvements in spectral regrowth and waveform quality in the application to an IS-95 reverse link signal are demonstrated.

A decomposition and reconstruction scheme for broadband modeling of on-chip passive components using the modified T-equivalent circuit topology

This paper presents a state-of-the-art technique for broadband modeling of on-chip passive components. The proposed decomposition and reconstruction methodology can efficiently and accurately establish the broadband SPICE model for an arbitrary multi-port reciprocal component over an extremely large bandwidth. The idea is to decompose a multi-port network into a number of one-port networks which can be lumped modeled simply and easily. Then a reconstruction process, based on the modified T-equivalent circuit topology, is invented to combine these one-port lumped models into a broadband multi-port model. In this modeling study, the S parameters for a series of passive components including spiral inductors, MIM capacitors, bifilar transformers and baluns, fabricated using a 0.18 /spl mu/m RF-CMOS foundry process, have been measured up to 20 GHz. The modeled S parameters agree quite satisfactorily with the measured results over the entire measurement frequency range.