Jean Andrian

CODE: Cooperative Medium Access for Multirate Wireless Ad Hoc Network

Cooperative communications can help combat fading and hence can significantly increase the capacity of wireless networks. Although various schemes have been proposed to leverage this capability, most of the current mechanisms require hardware modification. We present a novel MAC protocol for the multirate ad hoc network, called CODE, to entail simultaneous transmissions of unencoded information by multiple nodes to achieve the power gain of virtual antenna arrays. The key physical layer property that we exploit is an increased transmission rate due to the achieved power gain. Moreover, for bidirectional traffic, we jointly consider using network coding technique at the relay nodes to increase the system throughput. Our design is backward compatible with the IEEE 802.11 standard and only requires firmware upgrade, which is especially suitable for low-end terminals. Our evaluation in both analysis and NS-2 simulations show that CODE is able to improve the system throughput up to 60%.

Multilinear principal component analysis for face recognition with fewer features

In this study, a method is proposed based on multilinear principal component analysis (MPCA) for face recognition. This method utilized less features than traditional MPCA algorithm without downgrading the performance in recognition accuracy. The experiment results show that the proposed method is more suitable for large dataset, obtaining better computational efficiency. Moreover, when support vector machine is employed as the classification method, the superiority of the proposed algorithm reflects significantly.

Bit Error Rate Analysis of jamming for OFDM systems

The bit error rate (BER) analysis of various jamming techniques for orthogonal frequency-division multiplexing (OFDM) systems is given in both analytical form and software simulation results. Specifically, the BER performance of barrage noise jamming (BNJ), partial band jamming (PBJ) and multitone jamming (MTJ) in time-correlated Rayleigh fading channel with additive white gaussian noise (AWGN) has been investigated. In addition, two novel jamming methods - optimal-fraction PBJ and optimal-fraction MTJ for OFDM systems are proposed with detailed theoretical analysis. Simulation results validate the analytical results. It is shown that under the A WGN channel without fading, the optimal-fraction MTJ always gives the best jamming effect among all the jamming techniques given in this paper, while in Rayleigh fading channel the optimal-fraction MTJ can achieve acceptable performance. Both analysis and simulation indicate that the proposed optimal-fraction MTJ can be used to obtain improved jamming effect under various channel conditions with low complexity for OFDM systems.

Thermal Imaging as a Biometrics Approach to Facial Signature Authentication

A new thermal imaging framework with unique feature extraction and similarity measurements for face recognition is presented. The research premise is to design specialized algorithms that would extract vasculature information, create a thermal facial signature, and identify the individual. The proposed algorithm is fully integrated and consolidates the critical steps of feature extraction through the use of morphological operators, registration using the Linear Image Registration Tool, and matching through unique similarity measures designed for this task. The novel approach at developing a thermal signature template using four images taken at various instants of time ensured that unforeseen changes in the vasculature over time did not affect the biometric matching process as the authentication process relied only on consistent thermal features. Thirteen subjects were used for testing the developed technique on an in-house thermal imaging system. The matching using the similarity measures showed an average accuracy of 88.46% for skeletonized signatures and 90.39% for anisotropically diffused signatures. The highly accurate results obtained in the matching process clearly demonstrate the ability of the thermal infrared system to extend in application to other thermal-imaging-based systems. Empirical results applying this approach to an existing database of thermal images prove this assertion.

A computational efficient iris extraction approach in unconstrained environments

This research introduces a noise-resistant and computational efficient segmentation approach towards less constrained iris recognition. The UBIRIS.v2 database which contains close-up eye images taken under visible light is used to test the proposed algorithm. The proposed segmentation approach is based on a modified and fast Hough transform augmented with a newly developed strategy to define iris boundaries with multi-arcs and multi-lines. This optimized iris segmentation approach achieves excellent results in both accuracy (2% error) and execution speed (≤0.5s / image) using a 2.4GHz Intel® Q6600 processor with 2GB of RAM. This 2% error is an Exclusive-OR function in term of disagreeing pixels between the correct iris considered by the NICE.I committee and the segmented results from the proposed approach. The segmentation performance was independently evaluated in the “Noisy Iris Challenge Evaluation”, involving 97 participants worldwide, and ranking this research group in the top 6.

Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components

In order to make cognitive radio systems a practical technology to be dep- loyed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of perfor- mance and energy consumption for mobile platform. In this paper we present a feasibili- ty study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called most frequently and requires intensive floating-point computation. Then, we used the Virtex5 Field-Programmable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as 2X speedup and 50% of overall energy reduction. We achieve this with an increase of the power consumption by no more than 0.68%. This demon- strates the feasibility of the proposed approach.

A Client-Server Architecture for Context-Aware Search Application

This paper develops a client-side context-aware search application which is built on the context-aware infrastructure. A context-aware architecture is designed to collect the mobile user’s context information, derive mobile user’s current context, distribute user context among context-aware applications, and support the context-aware applications. The context acquisition is centralized at the context server to ensure the reusability of context information among mobile devices, while context reasoning remains at the application level. Algorithms are proposed to consider the user context profiles. By promoting feedback on the dynamics of the system, prior user selection is now saved for further analysis expediting a subsequent search. A software-based proxy is set up at the client side which includes the context reasoning component. Implementation of such a proxy supports that the context applications are able to derive the user context profiles. To meet the practical demands required of a testing environment, a software simulation using Yahoo search API is provided as a means to evaluate the effectiveness of the design approach in a realistic way. The integration of user context into Yahoo search engines proves how context-aware searches can meet user demands for tailored services and products in and around the user’s environment.

A High-Performance On-Chip Bus (MSBUS) Design and Verification

This brief proposes a high-performance system-on-chip bus protocol termed the master-slave bus (MSBUS). Considering the inevitable tradeoff among area, throughput and energy efficiency, the control bus is developed as a low-cost and low-power bus, and the data bus is created as a high-throughput full-duplex bus with the feature of block data transfer. To evaluate the bus performance, we create four analytical models including transfer time consumption (TC), wire efficiency (WE), valid data bandwidth (VDB) and dynamic energy efficiency. Then, the advanced high-performance bus-, advanced eXensible interface (AXI)-, and MSBUS-based direct memory access (DMA) are developed as a case study of hardware implementation. It is observed that MSBUS DMA costs less hardware resources and achieves higher performance, especially in the block transfer mode. For instance, the results from both the analytical models and the practical tests show that the TC of MSBUS is close to 63% of the AXI, the WE and VDB of MSBUS are almost 2.3 and 1.6 times of the AXI respectively, and the energy consumption is half of AXI in the block transfer mode.

Depth-First Worst-Fit Search based multipath routing for data center networks

Modern data center networks (DCNs) often use multi-rooted topologies, which offer multipath capability, for increased bandwidth and fault tolerance. However, traditional routing algorithms for the Internet have no or limited support for multipath routing, and cannot fully utilize available bandwidth in such DCNs. In this paper, we study the multipath routing problem for DCNs. We first formulate the problem as an integer linear program, but it is not suitable for fast on-the-fly route calculation. For a practical solution, we propose the Depth-First Worst-Fit Search based multipath routing algorithm. The main idea is to use depth-first search to find a sequence of worst-fit links to connect the source and destination of a flow. Since DCN topologies are usually hierarchical, our algorithm uses depth-first search to quickly traverse between hierarchical layers to find a path. When there are multiple links to a neighboring layer, the worst-fit link selection criterion enables the algorithm to make the selection decision with constant time complexity by leveraging the max-heap data structure, and use a small number of selections to find all the links of a path. Further, worst-fit also achieves load balancing, and thus generates low queueing delay, which is a major component of the end-to-end delay. We have evaluated the proposed algorithm by extensive simulations, and compared its average number of link selections and average end-to-end delay with competing solutions. The simulation results fully demonstrate the superiority of our algorithm and validate the effectiveness of our designs.

A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology

A reduced interface and high performance embedded system architecture (MSBUS) is proposed in this paper. The control bus is low-cost and low-power, whereas the data bus is high-bandwidth and high-speed especially. In addition, a Universal Verification Methodology (UVM)-based performance evaluation methodology is proposed to estimate the hardware structures. In order to evaluate the bus performance, AHB, AXI and MSBUS DMA are implemented as a case study. The experimental results show that MSBUS DMA uses the least hardware resources, reduces energy consumption to a half of AHB and AXI in the block transfer mode, and achieves 3.3 times and 1.6 times valid bandwidth of AHB and AXI respectively. Moreover, the proposed evaluation methodology is effectively used with sufficient accuracy.