Jean Brun

Development on wafer level anisotropic conductive film for flip-chip interconnection

With the fast growth of multimedia, the packaging has to satisfy high interconnection density, high data throughput, miniaturization, easy thermal management and reliability needs while keeping a low cost. Flip-chip, which probably offers the best solution to meet these requirements, has been chosen by major companies in various configurations: FCOB (flip-chip on board), WLCSP (wafer level chip scale package) and WLP (wafer level packaging). Flip-chip interconnection using micro-balls is a common interconnection technique and major developments are being carried out on wafer bumping. In this paper, a new bumping approach on the IC wafer with z-axis ACF (anisotropic conductive film) is presented. This WL-ACF concept proposes a universal solution for bumping as there is no specific rule design to be taken into account. Moreover, the z-axis ACF developed at CEA-LETI gives the possibility of achieving lower pitch and pad area as well as good electrical contact and reliability. WL-ACF is evaluated on a specific test vehicle assembly and compared with localized micro insert bumping and hybridization with standard ACF.

Detailed Characterisation of Ni Microinsert Technology For Flip Chip Die on Wafer Attachment

Face to face interconnection is an important technology for the assembly of heterogeneously integrated systems, it permits the integration of technologies from disparate backgrounds and allows separate technology optimization prior to assembly. This paper reports work on the optimization of micro-insert technology, which allows the electrical connection between the two systems. Detailed electrical characterization of the technology has been benchmarked against acoustic microscopy and close correlations have been identified using a combination of these techniques. Process constraints identified in the course of this work have been identified and used in the optimization of the technology.

Microstructured Interconnections for High Security Systems

In many applications, the concept of taking two die from different technologies to create a complete system can be more cost effective than trying to integrate the two components together on the same substrate. There are economies of scale associated with this approach which enable volume production of such systems to be proposed for the future, particularly in areas where low cost and security is of paramount importance. This concept is very attractive for applications such as smart cards where special crypto processor chips need to be manufactured to ensure that as many as possible security features that are needed for the application are present on board the device. These can be expensive to design and build and no matter what security aspects are put in place on chip, hackers can find a way to extract some of the information from the system. A novel approach to building in security to these systems is proposed in this paper

System-on-Wafer: 2-D and 3-D Technologies for Heterogeneous Systems

System integration, performance, cost and enhanced product functionality form the major driving forces behind contemporary innovations in packaging. The need for miniaturization has led to new architectures which combine a whole range of different technologies. The ultimate miniaturization goal is to incorporate all of the elements necessary to build the system in the same package. This approach of system-in-package faces two critical issues: the management of components from different sources and the cost of individual operations necessary to complete the package. Taking into account all the developments that have been made to date on wafer level packaging (WLP), it has been proposed to perform the packaging system at wafer level. Fully tested bare dice are integrated onto or into a wafer which can be pre-processed and post-processed using techniques such as micromachining, passive integration, plating of via and pad redistribution, bumping, dicing and testing. The principal objective of this paper is to present alternative technology for integrated dice coming from various foundries where design, die thickness and contact pad metallurgy are predefined. System integration at wafer level is presented and discussed in this paper. Different approaches, such as system-on-wafer (SoW) or rebuilding a wafer, are introduced and a technology status report is drawn up.

Reliability characterization and process optimization of Ni-based microinsert interconnections for flip chip die on wafer attachment

In many complex systems under development, the cost of integration and the compromises in performance that can result from the integration process can become prohibitive. Therefore, the establishment of a technology which enables the system level integration of devices from different technological families at the package level can become very attractive. In particular, since each component can be built in its optimum technology flow and interconnections within the package tend to be very short, very high performance can be achieved. The work to be presented in this paper describes direct and electrical reliability measurements of test structures used to optimise the electrical performance of micro insert based interconnection system as a function of flip chip mounting parameters. Micro-inserts have a great deal of potential for the face to face interconnection of stacked systems in three-dimensional integration technologies.

3D via belt technology

Three-dimensional die stacking with vertical interconnections through Si dies is potentially the best semiconductor system integration technique. With its incredibly promising improvements in speed and power dissipation in ICs, it has attracted increased attention in recent times. But this approach needs to perform through silicon vias at wafer level step and such wafers are not always available. This paper presents a 3D solution for interconnection of a base wafer with standard dies. Firstly, it consists in manufacturing copper pillars dedicated to vertical connection and manufactured around flip-chip position by electroplating. Then dies are connected to the substrate face-down by μ-insert technology. In order to obtain a new surface, the wafer is embedded in a polymer and planarized by grinding enabling copper pillars to be connected. A new rerouting and interconnection system enables a second die hybridization. This report presents the first manufacturing approaches and electrical results.

Reliability Characterization of Ni-based Microinsert Interconnections for Flip Chip Die on Wafer Attachment and Their Evaluation in Multichip SIMCARD Prototype

Face to face interconnection is an important technology for the assembly of heterogeneously integrated systems; it permits the integration of technologies from disparate backgrounds and allows separate technology optimization prior to assembly. This paper reports work on the optimization of micro-insert technology, which allows the electrical connection between the two systems. SimCard Prototypes have been developed and evaluated in usual and moisture conditions.Thermal cycling of test structures between -40°C and + 85°C has been performed at wafer level and results indicate that the average resistance of the daisy chain observed between the two devices does not change. However, electrical yield of the structures under damping tests @85°C and 85% of humidity decrease significantly as a consequence of the glue degradation. However further damping tests have been realized on the final packaged cards without any deterioration of the prototype.

Characterization of a highly sensitive silicon based three-axial piezoresistive force sensor

Recently, several three-axial silicon based force sensors have been developed. To mimic human mechanoreceptors and give sense of touch to robots highly integrated and highly sensitive three-axial force micro-sensors are required. We have fabricated silicon based 3D force sensors with piezoresistive gauges. In this paper we present a new method of electrical sensitivity characterization using an equipment normally dedicated for standard wire bonding applications such as wire pull or bondings shear. The measurements have been validated with a Nanoindenter and a good correlation is obtained with Finite Element Modeling (FEM). A sensitivity of 0.8mV/V/mN under normal forces is measured, one of the highest sensitivity value reported in the literature for piezoresistive 3D force sensors.

Reliability Aspects of Microinsert Based Interconnection Technologies

Face to face interconnection is an important technology for the assembly of heterogeneously integrated systems, it permits the integration of technologies from disparate backgrounds and allows separate technology optimization prior to assembly. This paper reports work on the optimization of micro-insert technology, which allows the electrical connection between the two systems. Thermal cycling of wafers between -40degC and + 85degC has been performed at wafer level and results indicate that the average resistance of the daisy chain observed between the two devices does not change significantly. However, the standard deviation of the distribution increases slightly as a consequence of thermal cycling. Analysis of interconnect and contact resistance indicates that while metal interconnect resistance diminishes, possibly as a function of annealing effects and grain growth. The resistance of individual contacts between devices is increasing somewhat. These two phenomena are considered to be effectively canceling each other out to provide the macroscopic behavior reported above. An average contact resistance of 14 mOmega was observed in devices which had undergone almost 500 cycles (an increase of ~6 mOmega from the starting resistance.

UHF RFID transponder with miniaturized packaging and interconnection

This paper presents the design and demonstration of UHF RFID tags based on commercial chips with wafer-level packaging and direct die-to-wire interconnection. The packaging and connection technology is presented and shown to have the potential to be a low-cost industrial process. The performances of the processed dies are characterized and compared to a standard wirebonding technology, showing no significant difference. Finally, several tags are demonstrated and exhibit read range performances in good agreement with the theory.