Jean-Louis Boizard

Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization

In this work, we present the implementation in a reconfigurable architecture of a dense stereo vision algo- rithm based on census transform. Analyzing census transform algorithm we found that size and access memory could be reduced, which consequently also reduced the latency time. Furthermore, architecture resources are optimized and efficient thanks to binary operations and integer arithmetic used by census transform directly compatible with the FPGA. Final architecture is able to construct 130 dense disparity maps per second for each corresponding pair of stereo images. A performance analysis, among other three disparity map implementations and our architecture, shows that at the end, we propose a better trade off among performance, latency, logic elements and memory size. The optimization and the resource saving rend our architecture an interesting option to solve the problem of stereo vision in real time, quite used in autonomous navigation.

An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis

This article presents a reconfigurable architecture to calculate a dense disparity map of two stereo images based on census transform. This architecture is simplified and efficient as a result of binary operations and integer arithmetic used by census transform. Our architecture was prototyped using GAUT which is a practical tool to develop high-level synthesis. We take advantage of GAUT rapid prototyping to implement different architectures and to make a general comparison among them, that lets us to optimize the architecture, and at the same time, to improve the systems performance. The optimization and the resource saving rend our architecture an interesting option to solve the problem of stereo vision in real time, quite used in autonomous navigation.

Stereovision Algorithm to be Executed at 100Hz on a FPGA-Based Architecture

Michel Devy1 * , Jean-Louis Boizard2, Diego Botero Galeano3, Henry Carrillo Lindado4, Mario Ibarra Manzano5, Zohir Irki6, Abdelelah Naoulou7, Pierre Lacroix8, Philippe Fillatreau9, Jean-Yves Fourniols10, Carlos Parra11 1,2,3,5,6,7,8,10CNRS; LAAS; 7 avenue du Colonel Roche, F-31077 Toulouse Universite de Toulouse; UPS, INSA, INP, ISAE; LAAS-CNRS : F-31077 Toulouse 3,4,11Pontificia Universidad Javeriana; Carrera 7 No. 40-62; Bogota 9Delta Technologies Sud Ouest; 2 Impasse Michel Labrousse, 31036 Toulouse 1,2,3,5,6,7,8,9,10France 3,4,11Columbia

Real-time classification based on color and texture attributes on an FPGA-based architecture

The design and the implementation of algorithms on FPGA-based architectures, is a complex task, above all for image processing. Many vision applications (video monitoring, obstacle detection from a vehicle) require real time performance. This paper analyzes only a classical function involved in these applications: pixel characterization by an attribute vector, and pixel classification as belonging or not to an interest class. Typical attributes are color and texture. Color is described by the chrominance given by the a and b coordinates in the CIE-Lab color space. Texture is only computed from the L* coordinate, describing the local intensity variations in a neighborhood of every pixel. AdaBoost has been selected in order to learn how to classify every pixel from its attribute vector. From a learning data base, it is learnt off line how to select and combine a given number of weak classifiers; then, the classifier parameters are loaded on an FPGA-based kit. This paper proposes different architectures and presents some results obtained from images acquired from a robot, in order to classify a pixel as Ground or Obstacle.

New real-time structural health monitoring microsystem for aircraft propeller blades

This presents work done on the project “Blade Parameters Recording Microsystem” funded by the French research program FUI. It resulted in a fully operational recorder that can be embedded on a plane. This system allows blade monitoring to be conducted using computing algorithms. Using a top-down modelling method, this recorder can be adapted to any kind of blade. Herein, recorder was devised for a Transall plane blade. This device was used to record data in order to subsequently compute a real-time blade monitoring algorithm. The algorithm takes several blade parameters into account. The top-down modelling easily allows the algorithm parameters to be adapted to various blades.

Real-time architecture on FPGA for obstacle detection using inverse perspective mapping

This paper presents an embedded architecture to implement in real time the Inverse Perspective Mapping (IPM) algorithm. The IPM algorithm allows a robot to detect obstacles under the hypothesis that the ground is flat, and the definition of an obstacle being anything that has a height above the ground. This algorithm is based on modifying the cameras angle of view to remove the perspective effect for the ground plane. The algorithm is implemented using co-design techniques and validated on a Stratix 3 FPGA. Several approaches proposed to develop an architecture devoted to this algorithm, are compared. Finally the proposed methodology can be extended to many cameras. The algorithm was fully tested for one camera and partially tested for 4 cameras.