Jean-Louis Carbonero

Comparison between beryllium-copper and tungsten high frequency air coplanar probes

High frequency air coplanar probes using tungsten tips are now available for wafer probing with aluminum pads. Comparative study of the beryllium-copper and tungsten behavior is presented in terms of contact resistance values, stability and reproducibility. Finally, tungsten is demonstrated to be the best material for breaking the aluminum oxide over the pad to enable accurate high frequency probing.<<ETX>>

Behavioral modeling of WCDMA transceiver with VHDL-AMS language

This article presents the behavioral modeling of a WCDMA transceiver. The model has been developed in VHDL-AMS language. The WCDMA behavioral model is made of RF parameters like gain, impedance, IIP, leakages. The methodology used to develop this model is included in a top-down design flow. The model has been validated by the comparisons between simulation results and measurements on a silicon prototype

A New Loopback GSM/DCS Bit Error Rate Test Method On Baseband I/Q Outputs

The Bit Error Rate (BER) evaluation in one of the key parameters to reach QoS (Quality of Service) requirement of modern digital communication of the next generation (3 and 4G). This paper presents a new loopback BER Test (BERT) method based on measurements on baseband IQ outputs. The interest of this method is that it allows quantifying separately from digital stage, the RF stage influence on BER performances. This test principle has been validated introducing 4 instruments in the loop plus a GSM/DCS monochip as device under test. Unfortunately at the moment, one of the instruments capabilities limits the bit rate to one third of demodulation bandwidth, i.e. 200kHz. Replacing this instrument by a pure digital demodulator in the loop will eliminate this restriction in the future. So any kind of baseband IQ BERT could be performed using that method.

Optimising test sets for RF components with a defect-oriented approach

This paper is aimed at studying defect-oriented test techniques for RF components in order to optimize production test sets. This study is mandatory for the definition of an efficient test flow strategy. We have carried out a fault simulation campaign for a low-noise amplifier (LNA) for reducing a test set while maintaining high fault coverage. The set of production test measurements should include low-cost structural tests such as simple current consumption and only a few more sophisticated tests dedicated to functional specifications such as S parameters, noise figure (NF) or IP3.

Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach

This paper is aimed at studying defect-oriented test techniques for RF components in order to optimize production test sets. This study is mandatory for the definition of an efficient test flow strategy. We have carried out a fault simulation campaign for a low-noise amplifier (LNA) for reducing a test set while maintaining high fault coverage. The set of production test measurements should include low-cost structural tests such as simple current consumption and only a few more sophisticated tests, dedicated to functional specifications, such as S parameters, noise figure (NF) or IP3.

Choice of a high-level fault model for the optimization of validation test set reused for manufacturing test

With the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

In this paper we present a new architecture for audio analog-to-digital converters (ADCs) that includes a Built-in Self-Test (BIST) technique for the test of the signal-to-noise and distortion ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sine-wave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 mum CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB.

A BIST Scheme for SNDR Testing of ΣΔ ADCs Using Sine-Wave Fitting

Sigma–Delta (ΣΔ) modulators have made possible the design of high-resolution Analogue-to-Digital Converters (ADCs) with relaxed analogue circuitry precision by moving most of the design complexity to the digital domain. However, testing these ΣΔ ADCs is becoming a costly task due to trends towards high-resolution implementations and associated increase in samples required to extract key specifications. In this paper, we propose a Built-In Self-Test (BIST) technique for high-resolution ΣΔ ADCs. The technique, mostly digital, moves most of the test complexity to the digital domain, that is in-line with the philosophy of ΣΔ modulation. Both the test signal generation and the output response analysis are performed on-chip. The stimulus, a sinusoid encoded in a binary bit stream, is chosen to have very high quality in the bandwidth of the converter with the quantization error laying outside of the analogue modulator’s bandwidth. For the output response analysis, a sine-wave fitting algorithm is implemented on chip. For this, a digital sinusoidal stimulus of a very high precision is needed as a reference signal. In this paper, we generate this reference signal from the same input stimulus, by passing it through the digital filter already existing in the converter. Simulations results show the capability of this technique to obtain measurements of the SNDR (Signal-to-Noise-plus-Distortion Ratio) for a 16-bit audio ΣΔ ADC.

Comparison of Active and Passive Load-Pull Test Benches

Some load-pull test benches are developed at present time in different university laboratories. These characterization benches offer high capabilities and are well suited for the research activities. This paper presents the evolutions to apply the load-pull characterization technique issued from the research to the industrial world. This application involves choices to make. These ones are justified and detailed after descriptions of a research and an industrial load-pull characterization bench.

Automated Measurement Procedures of Three-Port and Four-Port Devices on Silicon Wafers

The development of telecommunication networks and wireless systems has led to a continually increasing market for RF integrated circuits. The CMOS and BiCMOS silicon technologies are particularly attractive for the fabrication of these circuits because of the good performance of their transistors coupled with the low cost of production. They allow the development of very complex RF integrated circuits (RF-VLSI) and open the gate to future systems on chip. Simulation of these advanced circuits requires high frequency characterization of elementary two-port devices. Nevertheless three-port and four-port measurements will represent a very interesting tool for characterization of active components like BJTs or MOSFETs, passive components like tees and crosses, or for characterization of crosstalk and coupling. A new method which allows measurements of three-port and four-port devices for the specific case of silicon wafer in an industrial environment has been developed. This procedure is based on the use of coaxial loads, microwave switches and it requires several SOLT calibrations. On wafer and off wafer parasitic elements have been analyzed and their effects on measurements are taken into account. The equipment, the measurement principle and the different steps of correction are presented in this paper. Finally, the procedure has been validated on experimental measurements of advanced MOSFETs and BJTs. Very satisfactory results have been obtained and BJT characterization is presented as an example.