Jean-Pierre Colinge

Junctionless multigate field-effect transistor

This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Substrate crosstalk reduction using SOI technology

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.

High-Temperature Performance of Silicon Junctionless MOSFETs

This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.

Subthreshold slope of thin-film SOI MOSFET's

Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films. Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel. For comparison, the subthreshold slope of transistors made in thicker films is also reported.

Reduction of kink effect in thin-film SOI MOSFETs

Numerical simulation is used to show that potential and electric field distribution within thin, fully depleted SOI devices is quite different from that observed within thicker, partially depleted devices. Reduction of drain electric field and of source potential barrier brings about a dramatic decrease of kink effect.<<ETX>>

Reduced electric field in junctionless transistors

The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present.

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.

An SOI voltage-controlled bipolar-MOS device

This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.

Silicon-on-insulator 'gate-all-around' MOS device

The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described.<<ETX>>