Jean-Pierre Le Normand
Centre national de la recherche scientifique
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Jean-Pierre Le Normand.
IEEE Transactions on Nuclear Science | 2011
Martin Zlatanski; Wilfried Uhring; Jean-Pierre Le Normand; D. Mathiot
A fully characterizable, 128-stage asynchronous Multiphase Delay Generator (MDG) integrated in standard 0.35 μm CMOS technology is presented. The circuit consists of a mirror Voltage-Controlled Delay Line (VCDL), driven by a Delay-Locked Loop (DLL), and an analog memory block. The master DLL ensures the stability over temperature and the absolute precision of the delay, whereas the mirror VCDL allows an asynchronous operation of the MDG with respect to the DLL reference clock. The memory block carries out a precise stage-to-stage delay and jitter characterization by analog sampling the state of the mirror VCDL upon an external request. Two versions of the circuit differing by their VCDL layout configurations were processed in order to compare their absolute time accuracy and jitter performance. In the first variant the two delay lines were laid out in an interlaced arrangement, whereas in the second, the mirror VCDL was positioned under the master VCDL. A maximal temporal dynamic range of 125 ps-1 ns was achieved. The single-stage delay variation with temperature was less than 1% over the 10-60°C range considered. The mean RMS jitter level per stage remained below 3% of the elementary delay over the entire dynamic range of the MDG for both circuit versions.
ieee international newcas conference | 2010
Martin Zlatanski; Wilfried Uhring; Jean-Pierre Le Normand; Chantal-Virginie Zint; D. Mathiot
In this work, a time-resolved imager with adjustable single row sampling rate from 1 GS/s to 7.14 GS/s fabricated in standard 0.35 µm SiGe BiCMOS technology is presented. The prototype consists of a vector of 12 photodetectors, a Transimpedance Amplifier (TIA) stage, a 128-deep analog sampling and storage block and a Voltage-Controlled Delay Line (VCDL) for sampling clock generation. The imager demonstrated a 6.7 ns Full Width at Half Maximum (FWHM) 532 nm laser pulse capture with very good accuracy and a 500 MHz 650 nm optical periodical wave acquisition at 7.14 GS/s.
Proceedings of SPIE | 2010
Wilfried Uhring; Jean-Pierre Le Normand; Virginie Zint; Martin Zlatanski
The conventional streak camera (CSC) is an optoelectronic instrument which captures the spatial distribution versus time of a ultra high-speed luminous phenomena with a picosecond temporal resolution and a typical spatial resolution of 60 μm. This paper presents two Integrated Streak Camera (ISC) architectures called MISC (M for Matrix) and VISC (V for Vector) which replicate the functionality of a streak camera on a single CMOS chip. The MISC structure consists of a pixel array, where the column depth together with the sampling rate determine the observation window. For proper operation, the image of the slit has to be spread uniformly over the rows of the imager. The VISC architecture is based on a single column of photosensors, where each element is coupled to a front-end and a multi-sampling and storage unit. The observation window is determined by the sampling rate and the depth of the memory frame. The measurement of a 6 ns FWHM 532 nm light pulse laser is reported for both ISCs. For the two architectures, the spatial resolution is linked to the size and the number of the photodetectors.
2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference | 2009
Martin Zlatanski; Wilfried Uhring; Jean-Pierre Le Normand; Virginie Zint
A stable, sub-nanosecond delay generator is presented. Integrated in conventional low-cost 0.35 µm CMOS technology, the circuit consists of a mirror delay line driven by a dual-loop Delay-Locked Loop (DLL) and a 128-deep analog frame memory. As a practical application of the delay generator, a completely new, high-resolution, Time-to-Digital Converter (TDC) concept is implemented on-chip. A simulated 20 ps resolution is achieved. A delay stability self-characterization mode was also integrated and showed a 1 GHz sine wave sampled at 8 Gs/s.
international conference on sensor technologies and applications | 2010
Martin Zlatanski; Wilfried Uhring; Jean-Pierre Le Normand; Chantal-Virginie Zint; D. Mathiot
In this paper, two architectures for high-speed time-resolved imaging circuits in (Bi)CMOS technology are presented. The first architecture adopts the traditional for the most silicon imagers matrix configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable to the slit of a streak camera, coupled to an amplifier stage and an analog memory. The paper focuses on the design of a single vector-based time-resolved imager and presents recent results from a prototype fabricated in standard SiGe BiCMOS 0.35 µm technology. The circuit demonstrated a 6.7 ns Full Width at Half Maximum (FWHM) 532 nm laser pulse capture with very good accuracy and a 700 ps FWHM 650 nm laser diode pulse acquisition at 12 × 7.14 Gs/s.
Integrated optics and photonic integrated circuits. Conference | 2004
F. Morel; Jean-Pierre Le Normand; Chantal-Virginie Zint; Wilfried Uhring; Y. Hu; D. Mathiot
In this paper, we present design and characterisation of a fast CMOS APS (active pixel sensor) imager for high-speed laser detection, which can replace streak cameras. It produces the intensity information as a function of one spatial dimension and time (I=f (x, t)) from a two spatial dimensions frame. The time information is obtained for the first prototype camera by delaying successively the integration phase for each pixel of the same row. The different noise sources of the APS sensors; such as shot noise due to the photo sensor, thermal noise and flicker noise due to the readout transistors, and the photon shot noise, are presented in order to determine the fundamental limits of the image sensor. The first prototype FAMOSI (fast MOS imager) consists of 64/spl times/64 active pixels. The simulation and experimental results show that a conversion gain of 6.73/spl plusmn/0.25 /spl mu/V/e has been obtained with a noise level of 87/spl plusmn/ 3 electrons rms. The power consumption of the chip is 25 mW at 50 frames/sec. The time resolution is 0.8 ns for this new concept of camera.
IEEE Sensors Journal | 2015
Martin Zlatanski; Wilfried Uhring; Jean-Pierre Le Normand
A streak-mode optical sensor in standard 0.35-μm SiGe BiCMOS technology is presented. The circuit consists of a column of 64 photodetectors coupled to a linear array of transimpedance amplifiers and a 128-deep analog sampling and storage unit. The sweep speed of the sensor is continuously adjustable from 125 ps/pixel to 1 ns/pixel through a closed-loop delay generator. The sensor reaches a total sampling rate of 512 GS/s and a vertical dynamic range of 59 dB. The measured temporal resolution is 465 ps at λ = 400 nm. At λ = 800 nm, this figure is degraded down to 600 ps due to the increased penetration depth of the incident radiation. In a post-processing phase, the frequency response of the system was equalized, allowing the sensor to exhibit sub-500-ps temporal resolution over the entire visible spectrum. The reported streak-mode optical imager is thus suitable for the recording of nanosecond-order transients over a large range of wavelengths and can be used in applications, such as fluorescence metrology, time-resolved spectroscopy, and optical tomography.
Proceedings of SPIE, the International Society for Optical Engineering | 2008
F. Morel; Chantal-Virginie Zint; Wilfried Uhring; Jean-Pierre Le Normand
The classical streak cameras use a vacuum tube making thus fragile, cumbersome and expensive. The FAst MOS Imager (FAMOSI) project consists in reproducing completely this streak camera functionality with a single CMOS chip. The advantages of on-chip functionalities lead to a power reduction, a lower cost and miniaturization. In this paper, we show the capabilities of a prototype fabricated in the AMS 0.35 μm CMOS process. The chip is composed of 64 columns per 64 rows of pixels. The pixels have a size of 20 μm per 20 μm and a fill factor of 47 %. The Chip FAMOSI implements an electronic shutter and an analog accumulation capability inside the pixel. With this pixel architecture, the sensor can work in single shot mode when the light pulse power is sufficient and in repetitive mode, i.e. it can measure a recurrent light pulse and accumulates the successive photo charges into an internal node, for low light pulse detection. This repetitive mode utilizes an analog accumulation in order to improve the sensitivity and the signal to noise ratio of the system. Characterizations under static and uniform illumination in single shot mode have been done in order to evaluate the performances of the detector. The main noises levels have been evaluated and the experiments show that a conversion gain of 4.8 μV/e- is obtained with a dynamic range of 1.2V. Moreover, the charge transfer characterization in single shot mode has been realized. It permits to know which potential must be apply to the charge spill transistor to obtain the whole dynamic of the output with a maximal transfer gain, what is primordial to optimize the analog accumulation. Finally, the dynamic operation of the sensors is exposed. Measurements show a sample time of 715 ps and a time resolution better than 2 ns. A 6 ns light pulse has been measured in single shot and in accumulation mode.
Proceedings of SPIE, the International Society for Optical Engineering | 2006
F. Morel; Chantal-Virginie Zint; Wilfried Uhring; Jean-Pierre Le Normand
High speed cameras use the interesting performances of CMOS imagers which offer advantages in on-chip functionalities, system power reduction, cost and miniaturization. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, we present a new imager called FAMOSI 2 which implements an electronic shutter and analog accumulation capabilities inside the pixel. With this kind of pixel and the new architecture for controlling the integration, FAMOSI 2 can work in repetitive mode for low light power and in single shot mode for higher light power. This repetitive mode utilizes an analog accumulation to improve the sensitivity of the system with a standard Nwell/Psub photodiode. The prototype has been fabricated in the AMS 0.35 μm CMOS process. The chip is composed of 64 columns per 64 rows of pixels. The pixels have a size of 20 μm per 20 μm and a fill factor of 47 %. Characterizations under static and uniform illumination in single shot mode have been done in order to evaluate the performances of the detector. The main noises levels have been evaluated and the experiments show that a conversion gain of 4.8 μV/e- is obtained with a dynamic range of 1.2 V. Moreover, the charge transfer characterization in single shot mode has been realized. It permits to know which potential must be apply to the charge spill transistor to obtain the whole dynamic of the output with a maximal transfer gain, what is primordial to optimize the analog accumulation.
Archive | 1998
Hervé Simon; Jean-Pierre Le Normand; Robert Perichon
In this article, two topologies of L-C parallel active resonators are presented. These circuits are realized in MMIC technology, using three transistors which could be MESFET, hemt or HBT. The survey of these resonators shows the possibility, by controling the values of a resistor and/or a capacitor, on the one hand, to tune the resonance frequency of these circuits, and on the other hand, to cancel out their losses so as to obtain negative conductance. Compact, lossless and narrow-band filters are then implemented using previous active resonators. To date, the use of mesfet technology has reduced the synthesis of such active filters in S-band and at X-band low frequencies. Now, however, hemt and HBT technologies allow the extension of their implementation to the whole X-band. This survey is illustrated by the simulated response of a 10 GHz filter with a 500 MHz 3 dB bandwidth. The mmic technology is a 0.2 μm hemt one. The simulated performances of this filter achieve a mean transmission gain of 0. 5 dB, with a reflection loss higher than 10 dB at 10 GHz,RésuméCet article présente deux topologies de résonateurs actifs à circuits LC parallèles trois transistors, en technologie MESFET, HEMT ou HBT. Il montre la possibilité, en agissant sur la valeur d’une résistance et/ou d’une capacité, d’une part de fixer la fréquence de résonance de ces circuits parallèles, et d’autre part de réduire leurs pertes jusqu’à obtenir une conductance négative. Ces résonateurs MMIC sont ensuite utilisés pour synthétiser des réseaux compacts de filtrage en échelle, de bande étroite et sans pertes. Tandis que l’utilisation d’une technologie mmic à base de transistors mesfet avait restreint, jusqu ’à présent, la synthèse de ce type de filtres aux fréquences de la bande S et aux fréquences basses de la bande X, l’emploi de transistors HEMT et HBT permet d’étendre leurs réalisations à toute la bande X. Cette étude est illustrée par la simulation d’un filtre centré sur 10 GHz, de bande passante 500 MHz, réalisé à partir d’une technologie hemt 0,2 [un. La réponse du filtre présente un gain de 0,5 dB et des pertes par retour meilleures que 10 dB dans la bande passante.