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Dive into the research topics where Jee-Youl Ryu is active.

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Featured researches published by Jee-Youl Ryu.


Sensors and Actuators B-chemical | 1998

Zinc oxide thin film doped with Al2O3, TiO2 and V2O5 as sensitive sensor for trimethylamine gas

Sung-Hyun Park; Jee-Youl Ryu; Hyek-Hwan Choi; Tae-Ha Kwon

Abstract To obtain a sensitive sensor for TMA gas, ZnO-based films were fabricated by a rf magnetron sputtering method using targets added with Al2O3, TiO2, or V2O5. The films were heat-treated at a temperature between 400°C and 800°C for 60 min in oxygen. It was found that the sensitivity and selectivity of the films for TMA gas at 300°C increased by doping with 4.0 wt% Al2O3, 1.0 wt% TiO2 and 0.2 wt% V2O5. The sensor with the doped film 120 nm thick and annealed at 700°C for 60 min in oxygen exhibited fairly excellent sensitivity and selectivity to TMA, and electrical stability. Upon exposure to odors from a mackerel, the sensor using this film could trace well its deterioration during storage.


Microelectronics Journal | 2015

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

Habib Rastegar; Jee-Youl Ryu

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS-NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1-10.6GHz frequency range to a 50-? antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13?m CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92mW of dc power. The CMOS LNA features a maximum gain of 10.24dB, 0.9-4.1dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8dBm at 6.3GHz.


international conference on future generation communication and networking | 2010

Programmable RF System for RF System-on-Chip

Jee-Youl Ryu; Sung-Woo Kim; Dong-Hyun Lee; Seung-Hun Park; Jung-Hoon Lee; Deock-Ho Ha; Seung-Un Kim

This paper proposes a new automatic programmable radio frequency (RF) system for a System-on-Chip (SoC) transceiver. We built a 5-GHz low noise amplifier (LNA) with an on-chip programmable RF system using 0.18-(m SiGe technology. This system is extremely useful for today’s RF IC devices in a complete RF transceiver environment. The programmable RF system helps it to provide DC output voltages, hence, making the compensation network automatic. The programmable RF system automatically adjusts performance of 5-GHz low noise amplifier with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to the unusual thermal variation or unusual process variation.


international conference on future generation communication and networking | 2010

Automatic Image Quality Control System

Jee-Youl Ryu; Sung-Woo Kim; Seung-Un Kim; Deock-Ho Ha

A new automatic image quality control system for TFT-LCD (Thin Film Transistor Liquid Crystal Display) applications is proposed. Image quality factors such as gamma adjustment, flicker, brightness, and contrast are enhanced by proposed algorithm and system. Developed system utilizes programmable 6-point matching algorithm with reference gamma curve and automatic power setting algorithm. Proposed system showed significantly reduced gamma adjusting time, reduced flicker, high contrast and much less average gamma error than conventional manual method.


Journal of Institute of Control, Robotics and Systems | 2009

Design of Robust Stability Maximizing PI Controller in Motor Parameter Variation

Nae-Soo Cho; Jee-Youl Ryu; Chul-Woo Park; Woo-Hyen Kwon

This paper propose a PI controller that maximizes the degree of stability using a stability in a simplified motor model the applies decoupling control. The PI controller gains are directly from the motor parameters, thereby reducing the element of trial and error, and, the Kharitonov equation was used to evaluate the robustness of the gains to changes in the motor parameters. In addition, the system poles are located in the same position, the proposed method can provide a fast response. The effectiveness of the proposed controller is verified by simulation results.


Journal of Institute of Control, Robotics and Systems | 2009

Development of Automatic Gamma Optimization System for Mobile TFT-LCD

Nae-Soo Cho; Jee-Youl Ryu; Chul-Woo Park; Woo-Hyen Kwon

This paper presents an automatic LCD gamma control system using gamma curve optimization. It controls automatically gamma adjustment registers in mobile LCD driver IC to reduce gamma correction error and adjusting time. The proposed gamma system contains Module-Under-Test (MUT, LCD module), PC installed with program, multimedia display tester for measuring luminance, and control board for interface between PC and LCD module. Proposed algorithm and program are applicable for most of the LCD modules. It is realized to calibrate gamma values of 1.8, 2.0, 2.2 and 3.0. The control board is designed with DSP and FPGA, and it supports various interfaces such as RGB and CPU. Developed automatic gamma control system showed significantly reduced gamma adjusting time of 240 sec. and much less average gamma error of 11% than 42h and 27% with conventional manual method. We believe that the proposed system is very useful to provide high-quality LCD and to improve production process.


Integration | 2018

A low-voltage low-power capacitive-feedback voltage controlled oscillator

Habib Rastegar; Saeid Zare; Jee-Youl Ryu

This paper introduces an LC voltage controlled oscillator (VCO) in current-reuse configuration where transistors are biased in subthreshold region to save power consumption. A capacitive-feedback technique is employed to increase the output swing above the supply voltage and potential ground. Two capacitively source-degenerated negative resistors are employed to reduce the losses of the on-chip inductors resulting in an improved phase noise. The proposed VCO is designed and fabricated in 130nm CMOS technology. The overall circuit including core VCO and two buffers are biased at low supply voltage of 0.9V that consumes 490W. The measured phase noise is 110 dBc/Hz at 1MHz offset. A very high FOMT of 199.3dBc/Hz has been achieved by including tuning range. The chip area is 0.6 0.8mm2. The capacitive-feedback technique causes to improve output swing under low power.Varactors in the capacitive-feedback causes a wide oscillation frequency range.N/PMOS transistors are in a cross coupled structure while sharing the same current.Phase noise and symmetry of the VCO are enhanced by using negative resistor.


Journal of Semiconductor Technology and Science | 2016

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

Habib Rastegar; Jee-Youl Ryu

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS g m -boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.


Journal of Semiconductor Technology and Science | 2016

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

Habib Rastegar; Jae-Hwan Lim; Jee-Youl Ryu

The linearization technique for low noise amplifier (LNA) has been implemented in standard 0.18-㎛ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient (g m2 ) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 ㏈ and noise figure (NF) of 2.3 ㏈ at 2 ㎓. The excellent IIP3 of 20 ㏈m and low-power power consumption of 5.14 ㎽ at the power supply of 1 V are achieved. The input return loss (S 11 ) and output return loss (S 22 ) are kept below -10 ㏈ and -15 ㏈, respectively. The reverse isolation (S 12 ) is better than -50 ㏈.


International Conference on Advanced Engineering  Theory and Applications | 2016

Design of Low-Power 24 GHz Voltage-Controlled Oscillator

Geun-Ho Choi; Habib Rastegar; Myeong-U Sung; Shin-Gon Kim; Murod Kurbanov; Pushpa Chandrasekar; Jae-Hwan Lim; Jee-Youl Ryu

This paper proposes a 24 GHz voltage-controlled oscillator (VCO) for the short range automotive collision avoidance radar. A low power and small area in fully-differential configuration has been proposed. The proposed circuit is implemented using TSMC 0.13 µm mixed signal/RF CMOS process, and it is powered by a 1.5 V supply. The overall circuit with core VCO and two buffers is biased at the low supply voltage of 0.9 V. The fabricated VCO showed very low power dissipation of 5.5 mW and tiny chip area of 0.0576 mm2 at the operation frequency of 24 GHz as compared to conventional research results.

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Seok-Ho Noh

Andong National University

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Habib Rastegar

Pukyong National University

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Jae-Hwan Lim

Pukyong National University

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Shin-Gon Kim

Pukyong National University

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Geun-Ho Choi

Pukyong National University

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Woo-Chang Choi

Pukyong National University

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Sung-Woo Kim

Pukyong National University

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Chul-Woo Park

Kyungpook National University

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Deock-Ho Ha

Pukyong National University

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Hyek-Hwan Choi

Pukyong National University

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