Jeffrey A. Weldon

Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells

In massively parallel computational tasks, such as pattern recognition, conventional computing architectures have insufficient power efficiency for energy constrained environments. This has made alternative architectures, such as neuromorphic computing, increasingly attractive. Oscillatory neural networks (ONNs) are one promising architecture, but efficient hardware implementations have been limited by shortcomings in CMOS technology, specifically in the efficient implementation of oscillators and synaptic weights. The authors have recently demonstrated that metal-oxide based resistive switching (RRAM) structures can be engineered to create low-power, scalable, voltage-controlled oscillators that utilize inherent meta-stability in the device. This work proposes an RRAM-based ONN that couples oscillatory “neurons” through weighted “synapses” using oscillator phase as the state-variable. This paper demonstrates a robust architecture using only a few logic gates per neuron to implement phase initialization and locking of these oscillators, and demonstrate their capability to identify stored patterns from noisy inputs. Using measured characteristics of RRAMs as oscillators and programmable resistors, compact models are derived and used to simulate both an 8-neuron and 20-neuron network.

Phase Coupling and Control of Oxide-Based Oscillators for Neuromorphic Computing

Neuromorphic computing using neural network hardware has attracted significant interest as it promises improved performance at low power for data-intensive error-resilient graphical signal processing. Oscillatory neural networks (ONNs) use either frequency or phase as state variables to implement frequency-shift keying (FSK)- and phase-shift keying (PSK)-based neural networks, respectively. To make these ONNs power and area efficient, back-end-of-the-line compatible, and capable of processing multilevel information, we explore an emerging class of oscillators that show fine-grain frequency-tuning and phase-coupling. We examine TaOx- and TiOx-based oscillators (resistive random access memory-type) as elements of a neuromorphic compute block and experimentally demonstrate: 1) frequency control over four decades using a ballast MOSFET; 2) variable phase coupling between oscillators; and 3) variable phase programming between oscillators coupled with a MOSFET. Such fine-grain control over both frequency and relative phase serve as the desirable characteristics of oscillators required for multilevel information processing in star-type directly coupled FSK- and PSK-based neuromorphic systems that find applications in gray-scale image processing and other graphical compute paradigms. These attributes combined with the small size (<;1 μm2) and simplicity, make these devices attractive candidates for realizing large-scale neuromorphic systems at reasonable size and power.

High performance, integrated 1T1R oxide-based oscillator: Stack engineering for low-power operation in neural network applications

Brain-inspired non-Boolean computing paradigms are gaining wide interest due to their error resilient nature and massive parallelism. This work explores oxide-based compact oscillators for oscillatory neural networks (ONN). We demonstrate for the first time, best in class high-frequency performance at 500 MHz and low power (<; 200 μW). The superior figures of merit are achieved due to device engineering to give maximum swing at low power and integration as a 1T1R structure. We show frequency control over 2 orders of magnitude by varying the gate voltage and show its applicability to an ONN-based associative memory.

Design and Simulation of Piezoelectric-Charge-Gated Thin-Film Transistor for Tactile Sensing

This letter reports on an electronic device that can work as a tactile force sensor with a high spatial resolution and sensitivity. It integrates a thin-film piezoelectric sensor with a thin-film transistor (TFT) to form a dual-gate force-sensitive TFT. The piezoelectric sensor acts as a top-sensing terminal, which is charge-gated. An analytical model of the device is given to elaborate how the output current varies with the applied force, and a numerical study is conducted to evaluate its sensitivity, noise, and dynamic range. The integrated sensor can be potentially pixelated to form a high-resolution tactile sensor array, promising for electronic skin applications.

An RRAM-based Oscillatory Neural Network

Oscillatory Neural Networks (ONNs) are an intriguing brain-inspired paradigm for massively parallel computing, but implementations in CMOS fail to produce competitive architecture performance. While representing each artificial neuron with a CMOS oscillator does not scale well in terms of power and area, we have recently demonstrated the design and fabrication of low-power, small-area voltage controlled oscillators based on metal-oxide resistive devices (RRAMs). The same RRAM materials have also been demonstrated as programmable nonvolatile resistors for use as artificial synapses [1]. In this paper, we propose a RRAM-based ONN that is based on the coupling of oscillatory “neurons” through weighted “synapses.” A few CMOS logic gates per neuron are required for the phase detection that is used to initialize the input pattern and lock to the correct stored pattern. Using measurement data for RRAM-based oscillators and synapses, compact models were derived and characterized for use in simulating an eight neuron proof-of-concept network.

Analytical modeling of piezoelectric charge gated thin film transistor for force sensing and energy harvesting

This paper addresses a novel electronic device that works in force sensing and energy harvesting dual modes. It combines a dual-gate thin film transistors (TFT) and a thin film piezoelectric material. In force sensing mode, the thin piezoelectric film is placed atop TFT and works as a top gate. That top gate voltage which is induced by the applied force will affect the output current of TFT. An analytical model is given to elaborate how output current varies with applied force. Energy harvesting mode can be achieved by simply connecting the top, bottom gates and the drain terminals that will make TFT work in the saturation region without any other external power supply. A detailed analysis on working principle and numerical study is conducted to evaluate its theoretical energy generation in one cycle with various forces.

A wideband RF receiver with >80 dB harmonic rejection ratio

In this paper a wideband RF receiver with harmonic rejection (HR) is presented. Both gain mismatch and phase mismatch of the HR mixer have been calibrated independently using a digital calibration scheme. After calibration, both the 3rd order harmonic rejection ratio (HRR) and the 5th order HRR are greater than 80 dB and 70 dB respectively. The phase mismatch that leads to even order distortion is also calibrated to greater than 80 dB HRR. The calibration performed at 750 MHz is further observed being effective in more than 2 octaves of bandwidth with greater than 70 dB HRR. The receiver was manufactured in 65nm CMOS technology, occupying 0.72 mm2. Input RF frequency range is 0.15 GHz to 1 GHz and the receiver consumes 64 mW at 1 GHz. Noise figure is 3.2 dB and out-of-band IIP3 is -7 dBm at a total gain of 48 dB.

Low-power, high-performance S-NDR oscillators for stereo (3D) vision using directly-coupled oscillator networks

We have successfully demonstrated, a best in class low-power, high-performance S-NDR oscillator (benchmarked in Table I) through novel & unique material-engineering of leakage, endurance and by improving SNR through parallel-locking. These oscillators were then connected in form of a dense array that utilized unique array properties to simulate a full stereo-vision system. The system was found to consume 100× lower energy while being 16× better in performance (Table II), when compared to a conventional implementation purely based on computation.

Ultracompact Graphene Multigate Variable Resistor for Neuromorphic Computing

Brain-inspired or neuromorphic computing has been proposed as a method to overcome the limitations of the von-Neumann architecture. Neuromorphic computing relies on an array of neurons interconnected locally through synapses to perform computing functions such as pattern recognition and image processing. Neuromorphic computing with CMOS-based circuits has limited utility due to the relatively large area required by neurons and synapses, limiting the size of the neuromorphic network implementable on chip. In this paper, we present a novel ultracompact graphene variable resistor that can be used to implement both neurons and synapses. To illustrate the functionality of the proposed devices, we present a 3-bit digitally controlled synapse prototype that occupies 3 μm × 9.3 μm. The proposed devices pave the way for high-performance large neuromorphic networks that can be integrated with CMOS to augment its functionality or for beyond CMOS computation.

Analog neuromorphic computing enabled by multi-gate programmable resistive devices

Analog neural networks represent a massively parallel computing paradigm by mimicking the human brain. Two important functions that are not efficiently built by CMOS technology for their practical hardware implementations are weighting for synapse circuits and summing for neuron circuits. In this paper we propose the use of tunable analog resistances, such as multi-gate graphene devices, to efficiently enable these two functions. We design and demonstrate a complete analog neuromorphic circuitry enabled by such devices. Simulation results based on Verilog-A compact models for graphene devices confirm its functionality. We also provide experimental demonstration of our proposed graphene device along with projected circuit performance based on scaling targets. Our proposed design is suitable not only for the device example shown in this paper, but also for any beyond-CMOS technology that exhibits similar device characteristics.