Jeffrey Lam

Detection of solder bump marginal contact resistance degradation using 4-point resistance measurement method

Wafer Level Chip Scale Packaging (WLCSP) involves more bumping process steps after receiving the passivated product wafer from the foundry manufacturing line. As wafer sort is usually tested after the bumping process, on the solder bump, any process drift during bumping, especially the contact resistance degradation at the Aluminum (Al) pad to Redistribution Layer (RDL) interface or RDL to solder bump interface, can also lead to severe yield loss. In such situations, foundries still play a critical role in working with the bump house to determine the cause of failure. This paper describes three case studies on how the four-point resistance measurement method was employed effectively on the failure pad to accurately detect a marginal increase in bump stack resistance resulting in yield loss and to further localize the root cause of high interface contact resistance.

Fault isolation on marginal failures using dummy signals

Todays complex integrated circuits demand tight process control in manufacturing. In this paper, several case studies due to slight process deviation resulting in yield loss from marginal leakage failure were presented. While conventional fault isolation approach relies on the localization of exclusive laser induced or photon emission hotspot to highlight the defect location and pays little attention on intrinsic or dummy signals which are observable on reference units, the case studies described presented a different perspective of analyzing the slight difference in these dummy signals together with layout and circuit understanding to identify these subtle defects in the absence of exclusive hotspots.

Uncovered the “hidden real defect” masked by “other anomaly seen” through deep dive FA in wafer fabrication

In wafer fabrication, it is important for analyst to be equipped with the mindset of deep dive towards uncovering the underlying “hidden and real” defect even after finding some anomaly that appears to be the root cause. This is critical as inexperience analyst may regards the 1st anomaly seen as the cause of the low yield issue and this will lead to wrong process fix by the process integration. In this paper, we will discuss on 2 case studies to illustrate the beauty and importance of deep dive FA towards uncover the “hidden real defect” as masked by other anomaly seen first during the analysis. It will illustrate how failure analysis continues from analyst own thought to embark the root cause.

Failure analysis methodology on center patch issue due to salicidation in wafer fab

Failure Analysis (FA) consists of fault verification, isolation, defect tracing, characterization and physical (elemental) analysis. It helps wafer fab to understand the root causes of low yield cases, drive the yield improvement activities. Due to the complexity of modern Integrated Circuits (ICs), defects causing the failure need more effort, a variety of FA tools to be identified. In this case, a case of wafer center patch failure was studied. First of all, failure mode was identified through datalog study, which identified the majority of the center dies failed in leakage bin. The subsequent electrical fault isolation was performed by IV measurement and Thermal Induced Voltage Alteration (TIVA). The defect signal was found at unique structure for different failure dies, which was known to be poly resistor structure after layout study. After that, top-down physical analysis was then carried out using several FA techniques such as delayering, Scanning Electron Microscope (SEM) inspection, Passive Voltage Contrast (PVC), Atomic Force Probing (AFP), cross-sectional approach was also carried out using Focus Ion Beam (FIB) and Transmission Electron Microscope (TEM). In the end the defect was found to be unwanted salicadation at the side wall of the poly resistor, due to process-related issue. With the help of FA findings, Fab was beneficial in identifying the related process causing this faiure.

Failure analysis methodology on donut pattern failure due to photovoltaic electrochemical effect

Abstract This paper described a low yield case which resulted in a donut shape failing pattern. It also described a scenario where static fault localization is ineffective and a systematic problem solving approach based on symptoms, induction, hypothesis and verification was engaged to resolve the issue with understanding on the root cause and the failure mechanism. The low yield is due to residual light in the dilute HF clean tool which results in photovoltaic electrochemical effect on the exposed metal, through via holes, connecting to large PN junction. This results in subsequent resistive via formation and analogue failure.

Failure analysis on MEMS resonator device in wafer fabrication

This paper demonstrates a new de-process flow for MEMS resonator DRG (dc Resistance to Ground) failure analysis, using electrical fault isolation tool of TTVA to locate the defect site. After all, cutting method was performed to de-process MEMS from Si Cap, followed by SEM inspection to successfully observe the physical defect point. Auger analysis was then carried out on the defect point to identify the element contains, hence the root cause of preventing of Carbon and Mo was confirmed.

Static fault localization on Memory failures using Photon Emission Microscopy

Conventionally, Static Random Access Memory (SRAM) failures rely on memory bitmap for failure analysis. Static fault localization approach is ineffective except if the defect is large enough to cause a resistive short between the VDD and VSS nodes. However, it was observed that subtle defects that fall in the wordline (WL) of the pass gate transistor results in a partially turned-on NMOS with electroluminescence that can be effectively localized by Photon Emission Microscopy (PEM). In this paper, we leverage on this phenomenon to showcase 4 cases where static fault localization using PEM has helped the foundry to resolve memory BIST yield loss on advanced technology node devices without bitmap capability.

Defect localization enhancement using light induced CI-AFP

This paper describes the effectiveness of using light induced Current Imaging - Atomic Force Microscopy (CI-AFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and non-gated diode, as a result enhanced localization of gate to source/drain short.