Jeffrey Raynor

Object detection system using SPAD proximity detectors

This paper presents an object detection system based upon the use of multiple single photon avalanche diode (SPAD) proximity sensors operating upon the time-of-flight (ToF) principle, whereby the co-ordinates of a target object in a coordinate system relative to the assembly are calculated. The system is similar to a touch screen system in form and operation except that the lack of requirement of a physical sensing surface provides a novel advantage over most existing touch screen technologies. The sensors are controlled by FPGA-based firmware and each proximity sensor in the system measures the range from the sensor to the target object. A software algorithm is implemented to calculate the x-y coordinates of the target object based on the distance measurements from at least two separate sensors and the known relative positions of these sensors. Existing proximity sensors were capable of determining the distance to an object with centimetric accuracy and were modified to obtain a wide field of view in the x-y axes with low beam angle in z in order to provide a detection area as large as possible. Design and implementation of the firmware, electronic hardware, mechanics and optics are covered in the paper. Possible future work would include characterisation with alternative designs of proximity sensors, as this is the component which determines the highest achievable accur1acy of the system.

A low light level sensor with dark current compensating pixels

In ultra-low light conditions the presence of dark current becomes a major source of noise for a CMOS sensor. Standard dark current compensation techniques, such as using a dark reference frame, bring significant improvements to dark noise in typical applications. However, applications requiring long integration times mean that such techniques cannot always be used. This paper presents a differential dark current compensating pixel. The pixel is made up of a differential amplifier and two photodiodes: one light shielded photodiode connected to the non-inverting input of the opamp and a light detecting photodiode connected to the inverting input of the opamp. An integrating capacitor is used in the feedback loop to convert photocurrent to voltage, and a switched capacitor network is present in parallel with the light shielded pixel, which is used to satisfy the output equation to compensate the dark current. The pixel uses 150 μm x 150 μm photodiodes and is fabricated in a standard 0.18 μm, 6M1P, CMOS process. The results show that the pixel is light sensitive and has a linear output as expected. However, the dark current is not predictably controlled. Further work will be carried out on the pixel design, and particularly the switched capacitor circuit, to determine the cause of the non-predictability of the pixel output.

Back-illuminated voltage-domain global shutter CMOS image sensor with 3.75µm pixels and dual in-pixel storage nodes

A 1024×800 image sensor with voltage-domain global shutter pixels and dual in-pixel storage is implemented in a 90nm/65nm back-illuminated (BSI) imaging process. The pixel has a 3.75μm pitch, achieves -80dB PLS operating in its correlated double sampling mode and has a maximum dynamic range in its high-dynamic range imaging mode of 102dB.

Low light signal detection using a high dynamic range, high responsivity image sensor with multiple sampling modes

This paper presents a high dynamic range imaging sensor for detection of low light level signals. The sensor utilises a 12x12 array of large 150μm x 150μm pixels. The readout circuitry allows for multiple readout options including; multiple sampling (which allows for techniques such as Correlated Double Sampling (CDS)) and Time to Digital Conversion (TDC) techniques, operated both independently and under the same integration period. Scope for test patterns is also present in the design. All samples taken from the pixels before during and after exposure are converted digitally through the use of a single slope ADC utilising a 10 bit DAC and a comparator. No sample and hold capacitor is present. 4x10 bit SRAMs (Static Random Access Memory) per pixel are utilised to record multiple samples, or act as a counter for the TDC mode of operation. The large dynamic range of the system is attributable to both the novel timing system implemented within the multiple sampling mode of operation and the TDC mode of operation (operated independently or intermittently within the same integration time), which combines the use of 4x10 bit SRAMs with the 10 bit DAC to produce a counter capable of monitoring the pixel signal over extremely long integration times; in this case up to 30 seconds.