Jen-Feng Chung
National Chiao Tung University
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Publication
Featured researches published by Jen-Feng Chung.
IEEE Transactions on Fuzzy Systems | 2006
Chin-Teng Lin; Chang-Mao Yeh; Sheng-Fu Liang; Jen-Feng Chung; Nimit Kumar
Fuzzy neural networks (FNNs) for pattern classification usually use the backpropagation or C-cluster type learning algorithms to learn the parameters of the fuzzy rules and membership functions from the training data. However, such kinds of learning algorithms usually cannot minimize the empirical risk (training error) and expected risk (testing error) simultaneously, and thus cannot reach a good classification performance in the testing phase. To tackle this drawback, a support-vector-based fuzzy neural network (SVFNN) is proposed for pattern classification in this paper. The SVFNN combines the superior classification power of support vector machine (SVM) in high dimensional data spaces and the efficient human-like reasoning of FNN in handling uncertainty information. A learning algorithm consisting of three learning phases is developed to construct the SVFNN and train its parameters. In the first phase, the fuzzy rules and membership functions are automatically determined by the clustering principle. In the second phase, the parameters of FNN are calculated by the SVM with the proposed adaptive fuzzy kernel function. In the third phase, the relevant fuzzy rules are selected by the proposed reducing fuzzy rule method. To investigate the effectiveness of the proposed SVFNN classification, it is applied to the Iris, Vehicle, Dna, Satimage, Ijcnn1 datasets from the UCI Repository, Statlog collection and IJCNN challenge 2001, respectively. Experimental results show that the proposed SVFNN for pattern classification can achieve good classification performance with drastically reduced number of fuzzy kernel functions.
biomedical circuits and systems conference | 2008
Wei-Chung Huang; Shao-Hang Hung; Jen-Feng Chung; Meng-Hsiu Chang; Lan-Da Van; Chin-Teng Lin
Blind source separation of independent sources from their mixtures is a common problem for multi-sensor applications in real world, for example, speech or biomedical signal processing. This paper presents an independent component analysis (ICA) method with information maximization (Infomax) update applied into 4-channel one-line EEG signal separation. This can be implemented on FPGA with a fixed-point number representation, and then the separated signals are transmitted via Bluetooth. As experimental results, the proposed design is faster 56 times than soft performance, and the correlation coefficients at least 80% with the absolute value are compared with off-line processing results. Finally, live demonstration is shown in the DE2 FPGA board, and the design is consisted of 16,605 logic elements.
international symposium on circuits and systems | 2008
Chun-Chieh Huang; Shao-Hang Hung; Jen-Feng Chung; Lan-Da Van; Chin-Teng Lin
We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances abetter signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 mum CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 muW under +1.5 V supply.
IEEE Circuits and Systems Magazine | 2005
Chin-Teng Lin; Chun-Lung Chang; Jen-Feng Chung
The cellular neural network (CNN) is a powerful technique to mimic the local function of biological neural circuits for real-time image and video processing. Recently, it is widely accepted that using a set of CNNs in parallel can achieve higher-level information processing and reasoning functions either from application or biology points of views. The authors introduce a novel framework for constructing a multiple-CNN integrated neural system called recurrent fuzzy CNN (RFCNN). This system can automatically learn its proper network structure and parameters simultaneously. In the RFCNN, each learned fuzzy rule corresponds to a CNN. Hence, each CNN takes care of a fuzzily separated problem region, and the functions of all CNNs are integrated through the fuzzy inference mechanism. Some online clustering algorithms are introduced for the structure learning, and the ordered-derivative calculus is applied to derive the recurrent learning rules of CNN templates in the parameter-learning phase. RFCNN provides a solution to the current dilemma on the decision of templates and/or fuzzy rules in the existing integrated (fuzzy) CNN systems. The capability of the RFCNN is demonstrated on the real-world vision-based defect inspection and image descreening problems proving that the RFCNN scheme is effective and promising.
international conference on neural information processing | 2009
Li-Wei Ko; I-Ling Tsai; Fu-Shu Yang; Jen-Feng Chung; Shao-Wei Lu; Tzyy-Ping Jung; Chin-Teng Lin
Online artifact rejection, feature extraction, and pattern recognition are essential to advance the Brain Computer Interface (BCI) technology so as to be practical for real-world applications. The goals of BCI system should be a small size, rugged, lightweight, and have low power consumption to meet the requirements of wearability, portability, and durability. This study proposes and implements a moving-windowed Independent Component Analysis (ICA) on a battery-powered, miniature, embedded BCI. This study also tests the embedded BCI on simulated and real EEG signals. Experimental results indicated that the efficacy of the online ICA decomposition is comparable with that of the offline version of the same algorithm, suggesting the feasibility of ICA for online analysis of EEG in a BCI. To demonstrate the feasibility of the wearable embedded BCI, this study also implements an online spectral analysis to the resultant component activations to continuously estimate subjects task performance in near real time.
international symposium on neural networks | 2004
Chin-Teng Lin; Shi-An Chen; Chao-Hui Huang; Jen-Feng Chung
We proposed a new index, which can be used to classify the texture image. Because of the adjustment of image capture device or the distortion of image capture, the texture image may be transformed. Usually those transformations included rotation and scale. The proposed method provides an algorithm to avoid those effects respectively. This approach is the combination of cellular neural networks and principle component analysis neural networks. This fact implies it is a feed-forward neural network, and it does not need any training set.
ieee international workshop on biomedical circuits and systems | 2004
Shi-An Chen; Jen-Feng Chung; Sheng-Fu Liang; Chin-Teng Lin
This paper proposes a novel CNN-based biological visual processing for hybrid-order texture boundary detection. The texture boundary detection is based on the first- and second-order features to model pre-attentive stage of human visual system. This system is implemented by using a parallel computing neural network, called cellular neural networks (CNN). This CNN design adopts the multi-layer architecture involving a 5/spl times/5 large neighborhood and is extended to be the 16/spl times/16 array size for image processing. The proposed circuit models have been verified and the proposed method can successfully detect the texture boundary in an image.
international symposium on circuits and systems | 2008
Chih-Wen Hsueh; Jen-Feng Chung; Lan-Da Van; Chin-Teng Lin
For an embedded processor, the cache design almost occupies half chip area and power consumption. According to Amdahls law, if the power consumption of cache memories is reduced, the embedded processor can significantly save much power. However, the cache misses result in the penalty of thousands of cycles waiting and power consumption due to increasing the number of external memory access. Based on the above reason, the phased cache design is proposed and can largely improve the power consumption which wastes a set-associative cache. In this paper, the embedded pipelining processor without stalling and low-power phase cache is practiced with high-level simulation to achieve high-performance and low-power design. As experimental results, the proposed phase cache can reduce 44% power consumption compared with traditional one-access-cycle cache and eliminate pipeline stalls incurred by phased cache with only 6% gate count overhead.
international workshop on cellular neural networks and their applications | 2005
Ying-Chang Cheng; Jen-Feng Chung; Chin-Teng Lin; Sheng-Che Hsu
This paper presents a novel robust image stabilization (IS) technique to find out local motion vectors in the image sequences captured. Our technique is based on a cellular neural network (CNN) algorithm, which tracks a small set of features to estimate the motion of the camera. Real-time and parallel analog computing elements are contained in the architecture of CNN. It is a regular two-dimensional array and connects with its neighborhood locally. To implement this algorithm on VLSI CNN, the adaptive-minimized threshold method is proposed to find quickly extract reliable motion vectors in plain images which are lack of features or contain large low-contrast area. Each size of CNN is set to 1/120 of an image. A background evaluation model is also developed to deal with irregular images which contain large moving objects. The experimental results are on-line available to demonstrate the remarkable performance of the proposed CNN-based motion technique.
asia pacific conference on circuits and systems | 2004
Jen-Feng Chung; Chin-Teng Lin
In this paper, a new application-driven digital signal processor, called LASP24 (low-cost application-driven speech processor, 24-bit data width), for speech and audio signal processing is designed. Two applications, MELP and reverberation algorithms, are performed on LASP24. The developed emulator can quickly verify these two algorithms. The design has been integrated in the total area of 6.5 mm2 by using UMC 0.18mum 1P6M technology and fabricated. The maximum clock frequency is about 100 MHz with a single 1.8V supply