Jenn-Dong Sun

A coding theory approach to error control in redundant residue number systems. I. Theory and single error correction

A coding theory approach to error control in redundant residue number systems (RRNSs) is presented. The concepts of Hamming weight, minimum distance, weight distribution, and error detection and correction capabilities in redundant residue number systems are introduced. The necessary and sufficient conditions for the desired error control capability are derived from the minimum distance point of view. Closed-form expressions are derived for approximate weight distributions. Computationally efficient procedures are described for correcting single errors. A coding theory framework is developed for redundant residue number systems, and an efficient numerical procedure is derived for a single error correction. >

A coding theory approach to error control in redundant residue number systems. II. Multiple error detection and correction

For pt.I see ibid., vol.39, no.1, p.8-17 (1992). The coding theory approach to error control in redundant residue number systems (RRNSs) is extended by deriving computationally efficient algorithms for correcting multiple errors, single-burst-error, and detecting multiple errors. These algorithms reduce the computational complexity of the previously known algorithms by at least an order of magnitude. >

On theory and fast algorithms for error correction in residue number system product codes

The authors develop a coding theory approach to error control in residue number system product codes. Based on this coding theory framework, computationally efficient algorithms are derived for correcting single errors, double errors, and multiple errors, and simultaneously detecting multiple errors and additive overflow. These algorithms have lower computational complexity than previously known algorithms by at least an order of magnitude. In addition, it is noted that all the literature published thus far deals almost exclusively with single error correction. >

A superfast algorithm for single-error correction in RRNS and hardware implementation

The modular algebraic structure of the residue number systems (RNS) leads to modularity and parallelism in the hardware implementation for the RNS-based arithmetic processor [1], [2]. Both modularity and parallelism are essential to fully utilize the very-large-scale integrated (VLSI) technology [3]. In this work, a superfast algorithm for correcting single residue errors in the RNS is developed with a slight increase in redundancy. Based on this algorithm and another recently proposed fast algorithm, two architectures are designed for their hardware implementation. The hardware complexity for this superfast algorithm isO(k) while the hardware complexity for previously known algorithms isO(k2). The performance of this new technique is compared to the previously known techniques in terms of computational speed and other criteria.

Strength of signal flow in circuit simulation and its application

Circuit simulation is important for circuit design communities. Relaxation-based algorithms have been proven to be faster and more flexible than the standard direct approach used in SPICE. Signal flow analysis of the simulated circuit is very important in using Relaxation-based algorithms. However, there is no specific research undertaken for it. This paper discusses signal flows in circuit simulation, which gives two definitions for the strength of signal flow (SSF), discusses how to calculate SSF, and proposes techniques to utilize SSF in one of the Relaxation-base algorithms, ITA (Iterated Timing Analysis). Experimental examples on digital as well as analog circuits are given to prove the value of exploiting SSF in circuit simulation.

The Backward-traversing Relaxation Algorithm for Circuit Simulation

This paper proposes a new relaxation-based circuit simulation algorithm that is more robust and efficient than traditional methods such as waveform relaxation (WR) and iterated timing analysis (ITA). The new method employs a brand new strategy to simulate: it simulates by performing depth-first search in the signal flow graph of simulated circuits. The new method flexibly schedules subcircuits for calculating according to converging situations of subcircuits, so it can achieve robustness as well as efficiency in dealing with various types of circuits. A circuit simulation program based on the proposed method has been implemented, and various circuits have been tested to justify its performance

Distributed Circuit Simulation by Using Backward-Traversing Waveform Relaxation

This paper describes methods to utilize the multi-core PC as well as computers connected by internet to perform MOSFET circuit simulations. The Combining Simulation Method (CSM) is the used parallel algorithm. This paper also presents an automatic method to partition the simulation jobs in CSM. All proposed methods have been implemented and tested. Experimental results justify pleasing effects of proposed methods.

Parallel Circuit Simulation by Using Simulation-on-Demand and Iterated Timing Analysis

This paper considers utilizing the popular ITA (Iterated Timing Analysis) algorithm in CSM (Combining Simulation Method) to do parallel large-scale circuit simulation. An automatic partitioning method for jobs of CSM is presented, in which the related load balancing issue is also discussed. All proposed methods have been implemented and tested. Experimental results justify pleasing effects of proposed methods.

Incremental Circuit and Sensitivity Simulations Using Iterated Timing Analysis Algorithm

This paper investigates incremental circuit/sensitivity simulations for large-scale MOSFET circuits using the well-known ITA (Iterated Timing Analysis) algorithm. Incremental simulation uses the result waveforms of previous simulation to fasten the simulation speed, which is quite advantageous in the practical incremental-modifying circuit design strategy. Most proposed methods have been implemented and tested to justify their advantages.

STWR Algorithm-based MOSFET and InterconnectSimulation Using Transmission Line Time Step Control and Parallel Computing

The large-scale circuit simulation for MOSFET circuits with interconnects has been investigated in this paper. Our strategy is to use the reinforced Selective-tracing Waveform Relaxation (STWR) algorithm that equipped with a transmission line calculator. Strengthening methods for STWR and accelerating methods for the embedded transmission line calculation has been proposed, including the time step control scheme and parallel computing. All proposed methods have been implemented and tested to justify their superior performance.