Jens Trommer

Dually Active Silicon Nanowire Transistors and Circuits with Equal Electron and Hole Transport

We present novel multifunctional nanocircuits built from nanowire transistors that uniquely feature equal electron and hole conduction. Thereby, the mandatory requirement to yield energy efficient circuits with a single type of transistor is shown for the first time. Contrary to any transistor reported up to date, regardless of the technology and semiconductor materials employed, the dually active silicon nanowire channels shown here exhibit an ideal symmetry of current-voltage device characteristics for electron (n-type) and hole (p-type) conduction as evaluated in terms of comparable currents, turn-on threshold voltages, and switching slopes. The key enabler to symmetry is the selective tunability of the tunneling transmission of charge carriers as rendered by the combination of the nanometer-scale dimensions of the junctions and the application of radially compressive strain. To prove the advantage of this concept we integrated dually active transistors into cascadable and multifunctional one-dimensional circuit strings. The nanocircuits confirm energy efficient switching and can further be electrically configured to provide four different types of operation modes compared to a single one when employing conventional electronics with the same amount of transistors.

Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors

A feasibility and performance study of electrically reconfigurable nanowire transistors with selectable pFET and nFET operations is presented. The challenges toward circuit implementation are evaluated based on transient simulations of logic circuits. A novel physical structure capable of computing a NAND as well as NOR function is introduced. The new approach provides a flexible platform to develop and test fine-grain reconfigurable circuits and systems.

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between pand n-functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including NAND/NOR, AND/OR, and XOR/XNOR, and compared them with classical implementations. Two 1-bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.

Reconfigurable Nanowire Electronics-Enabling a Single CMOS Circuit Technology

Reconfigurable nanowire transistors are multifunctional switches that fuse the electrical characteristics of unipolar n- and p-type field effect transistors (FETs) into a single universal type of four-terminal device. In addition to the three known FET electrodes the fourth acts as an electric select signal that dynamically programs the desired polarity. The transistor consists of two independent charge carrier injection valves as realized by two gated Schottky junctions integrated within an intrinsic silicon nanowire. The transport properties that provide unipolar n- and p-type behavior will be elucidated. Further, solutions to the major device challenges toward the implementation of these novel transistors at the circuit level are proposed, by exploiting specific nanowire geometries and dimensions. These include methods that deliver equal on-currents and symmetric transfer characteristics for n- and p-type, and that eliminate supra-linear output characteristics at low source-drain biases. We will further show that circuits built of these symmetric transistors successfully exhibit complementary operation. Finally, the prospects in building reconfigurable circuits and systems will be briefly summarized.

On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET

Dual-independent-gate silicon FinFET has demonstrated a steep subthreshold slope (SS) when a positive feedback induced by weak impact ionization is triggered. In this paper, we study the temperature dependency of the steep SS by characterizing the fabricated device from 100 to 380 K. The measured characteristics of SS show a reduced sensitivity to temperature as compared to conventional MOSFETs. Based on the temperature-dependent characterization, we further analyze the steep-SS characteristics and propose feasible improvements for optimizing the device performance.

Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits

We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors in series. This leads to topological differences and increased flexibility in circuit design. We found that especially complex functions, like Majority and Parity gates of many inputs, which are generally avoided in standard CMOS technology, benefit from the new device type. This can be exploited to directly map reconfigurable building blocks, e.g. dynamically switching NAND to NOR. Exemplary 6-functional logic circuits will be shown, which exhibit up to 80% reduction in transistor count, while maintaining the same functionality as compared to the CMOS reference design. Logical effort analysis indicates that 20% less circuit delay and 33% less normalized dynamic power consumption can be achieved.

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions

Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.

Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors

Mechanical stress is an efficient but rather unexplored performance booster for diverse emerging research devices based on tunneling phenomena, such as tunnel field-effect transistors (TFETs), resonant TFETs, and reconfigurable FETs. In this letter, stress profiles formed by self-limited oxidation of intrinsic silicon nanowires are applied exemplarily on device simulations of reconfigurable silicon nanowire transistor based on two independently gated Schottky junctions. The deformation potential theory and the multi-valley band structure are applied for modeling of stress-dependent Schottky barriers. Strained n- and p-type transistors are analyzed with respect to transfer the characteristic and the influence of each strain direction. It has been verified that mechanical stress is an effective option to control current injection through the Schottky junctions and thus to achieve symmetric performance of reconfigurable nanowire devices.

Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors

Mechanical stress has the potential to be an efficient performance booster for diverse emerging research devices based on tunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable FETs. The effect is highly dependent on the constellation between the stress source and the crystal orientation. Although stress engineering is well established for enhancement carrier mobility, it is rather unexplored for the control of tunneling. In this work stress profiles formed by four different sources are studied by device simulations of reconfigurable silicon nanowire transistor using two independently gated Schottky junctions. Self-limited oxidation of the intrinsic silicon nanowire is used as an example to describe the effects of mechanical stress on the multi-valley band structure applying the deformation potential theory and on the average effective tunneling mass. The transfer characteristics of strained n- and p-type transistors are analyzed with respect to the current ratio between electron and hole conduction which is important to implement reconfigurable CMOS circuits. It has been verified that mechanical stress formed by oxidation as well as stressed top layers are effective options to control the current injection through the Schottky junctions and thus to achieve symmetric operation of reconfigurable nanowire devices.

Exploiting transistor-level reconfiguration to optimize combinational circuits

Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free technology. However, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so far. In this paper, we present first steps to a new compact and efficient design of combinational circuits by employing transistor-level reconfiguration. We contribute new basic gates realized with silicon nanowires, such as 2/3-XOR and MUX gates. Exemplifying our approach with 4-bit, 8-bit and 16-bit conditional carry adders, we were able to reduce the number of transistors to almost one half. With our current case study we show that SiNW technology can reduce the required chip area by 16 despite larger size of the individual transistor, and improve circuit speed by 26%.