Jensen Tsai

Ag alloy wire characteristic and benefits

Gold wire has been high volume production in IC packaging industry. With soaring price of gold in recent years and IC packaging search for cost reduction, copper wire offers 2nd alternative for wire bonding type assembly. But copper wire has drawbacks in control issues such as pad crack, aluminum splash, cratering and low throughput, Cu wire need a more complex multi-processing program to solve above problems, even if copper raw material cost is low, that cause the process costs are increased These limitations of copper wire are related to pad thickness and structure. Silver alloy wire can emerge as 3rd alternative as the cost can compete with copper and the properties of silver are nearly identical to gold while in the die to die package which benefits will be more apparent Many Study had performed for Silver alloy wire (88% & 95%), included the general workability, wire pull, ball shear, Al splash, pad-to-pad bonding. To get good workability result, Silver alloy wire properties have been studied and done the DOE to determine the best material properties windows. The key properties included the element composition and elongation, hardness, etc. IMC is another key point for the reliability performance, with the DOE of best wire bonding parameters, the IMC structure was analyzed with different condition of lead-frame based, substrate based. Combined with process flow and compound material types, IMC behavior has been observed. Electron Migration study had been performed as well to check if any side effect for Silver alloy wire bonding. Experiment results showed Silver Alloy wire bonding has better performance than copper. Silver alloy wire can be the mainstream to replace gold and copper wire, especially in pad-to-pad wire bonding type.

Interconnection challenge of wire bonding — Ag alloy wire

Traditionally, gold wire has been high volume production in IC packaging industry. With soaring price of gold in recent years and the of cost-efficiency, copper wire offers an alternative for Microelectronic Assembly. But copper wire has drawbacks in process control issues such as pad crack, aluminum (Al) splash, cratering and low throughput. Those limitations of copper wire are related to pad weakness. (thickness and structures) Silver alloy wire can emerge as another alternative as the cost can compete with copper and the properties of silver are nearly identical to gold. Copper wire is not suitable for thin aluminum pad as pad cannot sustain the wire bonding force which causes pad crack, within the range of pad thickness less than 1.2um. Copper wire is not recommended for weak pad structure either, such as partial array via and Non-Via pad structure. Copper wire turns out to be a lower throughput due to slow Intermetallic (IMC) growth, especially at pad to pad bond, dropped down to 70%-80% compared to gold wire. Forward bonding has been proven no problem by copper wire, unless the exceptions mentioned previously. But pad-to-pad bond is not easy due to bond pad struck twice. Silver alloy wire can handle SSB bond well, especially thin Al pad and weak bond pad structures. All wire bonders obtained high throughput by using Ag wire compared to gold wire. In this paper, wire bonding BGA with stacked dies structure, the workability and reliability tests such as wire pull, ball shear, IMC coverage, crater and aluminum splash were conducted. Silver wire ends up with better performance than copper.

Challenges of Ultra-Thin 5 Sides Molded WLCSP

As mobile electronics are continuously driven for compact, slim and lightweight, miniaturization of IC packaging has been a must. There are increasing Wafer Level Chip Scale and fan-in Package (WLCSP) employed in electronics to achieve the miniaturization. Since WLCSP just is the Die with solder balls attached, WLCSP has the smallest footprint and the lightest weight compare to substrate base and lead-frame base package. However, WLCSP side wall with pure silicon is brittle, it is easily damaged and cracked during transportation and SMT processes. How to protect the WLCSP sidewall and to prevent the cracks is a rising issue for WLCSP applications. Therefore, as a molded WLCSP has aroused lots of attention in IC semiconductor industry. It not only provides side wall protection but also enhances package board level reliability by additional molding fixture around solder balls. By using a wafer form molding technology, it solves side wall crack issue and has no concern for high cost. Without rigid support and with unsymmetrical structure, the major challenges of this molded WLCSP come from the wafer warpage post backside grinding process. In order to diminish the warpage during backend processes, lots of experiments were conducted extensively to reduce the wafer warpage, including molding compound selection (which focus on its CTE and Tg adjustments), post-mold cure optimization, die thickness decision, and so on. In this paper, a test vehicle with ultra-low profile was evaluated. Stress simulation was conducted to determine the package construction and work out the bill of material. Screen and corner DOEs which includes molding compound selection and post-mold cure parameters were performed to come out the optimal material and process window. Functional test and Board reliability test have been passed as well. Additional collision test also shows good side wall protections. Hence five sides molded WLCSP has been proven to be a feasible and reliable way for the miniaturization in assembly industry.

Development for VCI (Vertical Circuit Interconnection) technology for stacked die package

Wire bonding technology has been the mainstream for stacked die packages for over five years. Yet, based on current design rule, the package body size increases with respect to the number of dice stacked in the package. Furthermore, the electrical performance is greatly dependant to the wire length. By applying Vertical Circuit Interconnection technology, VCI, the package footprint can be reduced to offer relatively smaller package size. As such, the electrical performance is enhanced due to shorter signal transmitting length.

A lead-frame pre-mold coreless substrate development

It is well-known that thick substrate core has obviously increased package thickness and also weakened device performance, including electrical and thermal points of view. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame with pre-molding compound techniques has aroused lots of attention in IC semiconductor industry. It has brought not only thin package and device performance benefits, but also tremendous cost down benefits. Compared with traditional lead-frame types of packages (such as QFN, QFP, and so on) with NO trace, the above coreless substrate with trace routing capability can effectively shrink package size to save PCB board space and also shorten wire length to improve device electrical performance. Moreover, its BGA solder ball can enhance better SMT yield & Reliability performance as well, which compared with no solder ball in traditional QFN and QFP packages. However, without rigid substrate core material supporting, package warpage becomes a dominant issue for coreless substrate. It has slowed down or even inhibited sometimes for people to introduce it into production. Therefore, a lot of development works for package warpage improvement were intensively studied in these years, including mold compound raw material selection(which focus on its CTE and Tg adjustments), mold compound cure process temperature optimization, and lead-frame layout density and metal thickness definition, and so on. In the long run, as a ultra low cost solution under certain conditions, the above coreless substrate with multi-trace layer and finer pitch of plating trace capabilities can be easily applied to replace not only wire-bonding FBGA (Fine pitch Ball Grid Array) low-end products, but also FCCSP high-end products In this study, besides its benefits and challenges are introduced, a lot of mechanical stress simulation models and DOE studies are also addressed how to effectively reduce package warpage and then eventually improve its SMT yield and reliability performance.

Development of a pre-mold lead-frame for multi-row QFN package

QFN and Dual row QFN (DR-QFN) are mature packages which the current industry can only provide IC assembly for body size less than 13×13mm, with less than 180 IO counts. At present, substrate with Ball Grid Array is often preferred as the market trend for more pin counts requisition. Yet, the cost of substrate is significantly higher than lead-frame. By applying the concept of trace routing in a conventional substrate to intermix with QFN lead-frame manufacturing process, an ordinary QFN package was then reborn to support for more IO pin counts and larger body size, which this multi-row QFN has a new name — enhanced QFN (eQFN, by SPIL). Apart from the standard etching and punching manufacturing process on a conventional lead-frame, the lead-frame for eQFN adopts plating process, such that it is similar to Cu plating of a substrate. The conventional drilling was replaced by photo and plating process, that makes the luxury of having 30um/30um line width/space not a concern for higher cost. A pre-mold process was employed to sustain the Cu trace within lead-frame, providing the physical strength for the resined strip to survive the rest of assembly process. By using such lead-frame, the number of IO could be increased up to 400 and the maximum body size extended to 15mm×15mm. Two test vehicles (body sizes range between 10×10mm to 15×15mm, IO counts range between 200 and 350) were studied. Affirmatively, the goal were achieved to replace current TFBGA with offering the same package outline and pin out as well as identical ball assignment. In this report, reliability and functional verification between the two package types were compared. Thus eQFN is the new package with breakthrough technology in place of current TFBGA under certain conditions.

Challenges of flip chip packaging with embedded fine line and multi-layer coreless substrate

As mobile electronics are continuously driven for compact, slim and lightweight, miniaturization of IC packaging has been a must. Coreless substrate with fine-trace embedded technology is a key to achieve package miniaturization. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layers to interconnect the chip and the PCB board. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate. Therefore, as a NEW innovative coreless structure, a substrate with the features of embedded trace has aroused lots of attention in IC semiconductor industry. Its trace is plated on a flat carrier and is embedded just after the plating. By using this unique embedded trace technology, it makes the fine-line of having 20um/20um or 15um/15um line width/space and having no concern for high cost. Without rigid core layer, the major challenges of this coreless substrate come from the warpage throughout substrate manufacturing and assembly process. In order to diminish the warpage during substrate manufacturing, prepreg (PP) was employed as the dielectric layer of a substrate. Furthermore the glass fiber in PP can reinforce the rigidity and flatness. For assembly process, lots of experiments were conducted extensively to reduce the package warpage, including molding compound selection (which focus on its CTE and Tg adjustments), post-mold cure optimization, die thickness decision, and so on. In this paper, a test vehicle (flip-chip package, 12x12mm2 body size, above 500 IO count) was carried out. 2layer and 3layer substrates were built for the different applications and were evaluated. Stress simulation was conducted to determine the package structure and work out the bill of material. Screen and corner DOEs which includes molding compound selection, die-bond reflow profile and post-mold cure parameters were performed to come out the optimal material and process window. Reliability and functional test have been passed as well. Hence coreless substrate with embedded trace technology has been proven to be a feasible and reliable way for the miniaturization in assembly industry.

Flip chip packaging with pre-molded coreless substrate

In the recent years, compact, slim and lightweight mobile electronics are requested from customers. Miniaturization of IC packaging has been a must. Coreless substrate technology is the key to achieve it. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layer to interconnect chip and the motherboard. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame and pre-molding compound techniques has aroused lots of attention in IC semiconductor industry. Its trace is plated on the metal carrier and is embedded by molding compound. By using this unique embedded trace technology, it makes the fine-line of having 20um/20um or 15um/15um line width/space and having no concern for high cost. However, without rigid substrate core material supporting, the major challenges of this coreless substrate come from the warpage throughout substrate manufacturing and assembly process. In order to diminish the warpage, lots of experiments were conducted and discussed in this paper. Thermal performance and mechanical stress simulations also were employed to establish the package structure and also to narrow down the row material selections, including die thickness decision, pre-molding and molding compound selection (which focus on its CTE and Tg adjustments). Screen and corner DOEs which includes molding compounds, die-bond reflow profile and post-mold cure parameters were performed to come out the optimal material and process window. Reliability and functional tests have been passed as well. Hence, this pre-molded coreless substrate has been proven to be a feasible and reliable way for the miniaturization in assembly industry.