Jensheng Huang

Identification of subresolution assist features that are susceptible to imaging through process

Sub-resolution Assist Features (SRAFs) are powerful tools to enhance the focus margin of drawn patterns. SRAFs are sized so they do not print on the wafer, but the larger the SRAF, the more effective it becomes at enhancing through-focus stability. The size of an SRAF that will image on a wafer is highly dependent upon neighboring patterns and models of SRAF printability are, at present, unreliable. Conservative SRAF rules have been used to ensure that SRAFs never print on a pattern. More accurate models of SRAF printing should allow SRAF rules to be relaxed, resulting in more effective SRAF placement and broader focus margins. The process models that are used during Optical Proximity Correction have never been able to reliably predict which SRAFs will print on a pattern. This appears to be due to the fact that OPC process models are generally created using data that does not include subresolution patterns. In addition, the definition of a printing SRAF is not clear, as it can range from a photoresist film left on a wafer to a pattern that is transferred to the substrate during the etch process. This paper will demonstrate a model that identifies SRAFs which appear in photoresist and those which survive the etch step.

The use of optical proximity correction to compensate for reflectivity differences in N type and P type poly- silicon

Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to fully control those interactions, different processes typically have variations that can cause significant deviation of the properties of printed integrated circuit. However, if a process variation is predictable and systematic, OPC techniques can successfully be applied to compensate for those process variations by modifying the layout. One such process variation relates to topographic variation on a wafer surface, which can cause defocusing during an optical lithography process. The nominal-focus aerial image of the layout should ideally be coincides with the wafer surface. In reality, topographic variation on the wafer surface can cause portions of the wafers surface to be deviated from the nominal focal plane. This can result in defocused aerial image on the wafer causing line width variation of transistor gates during manufacturing process. This problem can be minimized by using anti-reflective coatings as well as differential biasing of the n-type, n-type, and field polysilicon. However, even after application of these two techniques, some residual error remains because the ARC layers are not fully absorbent. Moreover, the biasing techniques also induce process problems at the transition point between the biases and unbiased gate regions. In fact, required applied biases gradually become difficult to manage during technology node migrations. This paper presents a system that accurately determines critical dimension layout by compensating for the effects of topography variation on the performance of an optical lithography process. In this study, a model form and its empirical calibration process have been presented.