Jeong Park

Measurement of temperature profiles on visible light-emitting diodes by use of a nematic liquid crystal and an infrared laser

We present a new technique for measuring the temperature profiles of visible LED chips by use of a nematic liquid crystal with IR laser illumination. The LEDs studied have a multi-quantum-well InGaN/GaN/sapphire structure. New features in this technique are the use of a high-power IR laser beam as the sensing light and the insertion of a color filter in the optical path to block the high-intensity LED light. For the LEDs measured, the conversion efficiency decreases by 70% when the junction temperature rises from 25 to 107 degrees C. This technique is a valuable tool for studying the performance of LEDs as a function of junction temperature.

Temperature measurement of visible light-emitting diodes using nematic liquid crystal thermography with laser illumination

In this letter, we present a new configuration with laser illumination to measure the temperature of visible light-emitting diode (LED) chips using nematic liquid crystals. This method is applied to measuring the junction temperature of multiquantum well (MQW) LEDs in InGaN-GaN-sapphire structure. A color filter is inserted in the optical path to attenuate the overwhelming LED light. A high-power laser beam is used as the sensing light to enhance the contrast of the thermal image on LED chips. This technique is nondestructive and can be performed in real-time during device operation. One objective is to investigate the effect of the junction temperature on the electrical and optical performance of the LED devices. For the LEDs measured, the conversion efficiency decreases by 67% when the junction temperature rises from 22/spl deg/C to 107/spl deg/C. The new measurement configuration is a valuable tool to study the thermal performance of GaN-based LED devices and subsequently to investigate the degradation on electrical and optical performance due to junction temperature increase.

Thermal modeling and measurement of GaN-based HFET devices

In this letter, we present our thermal study results of GaN-based heterojunction field effect transistors (HFETs). In thermal computation, PAMICE code was used to calculate temperatures in a three-dimension (3-D) model. In the thermal measurement, nematic liquid crystal thermography was employed to determine the peak temperature on the surface of the device chip. The calculated and directly measured temperatures agree well. These methods are valuable in predicting the thermal performance of GaN-based HFET devices, in particular the power devices.

An electrical model with junction temperature for light-emitting diodes and the impact on conversion efficiency

We present an electrical model for quantum-well light-emitting diodes (LEDs) with a current-spreading layer. The LEDs studied have a multiquantum well (MQW) between p-GaN and the n-GaN grown on sapphire. The model consists of a diode connected with a series resistor resulting from the combined resistance of the p-n junction, contacts, and current spreader. Based upon this model, the I-V curve of the diode itself without the series resistance is extracted from the measured LED I-V curve. The model also includes an empirical diode current equation which was sought by matching the extracted I-V curve. In the seeking process, junction temperature (T/sub j/) rather than case temperature (T/sub c/) was used in the equation. The diode model allows one to calculate the reduction on conversion efficiency caused by the series resistor. Results show that the current-spreading layer causes 20% of the efficiency reduction at T/sub j/=107/spl deg/C.

Thermal modeling and measurement of AlGaN-GaN HFETs built on sapphire and SiC substrates

We present thermal modeling and measurement results of AlGaN-GaN heterojunction field effect transistors fabricated on sapphire and SiC substrates, respectively. The device structures are identical except for the substrate material used to grow the AlGaN-GaN heterostructure. One objective is to study the effect of substrate material on the thermal and electrical performance of the resulting devices. To compute the temperature profiles, in-house PAMICE code developed for a three-dimensional structure was used. To measure the temperatures on the chip surface, nematic liquid crystal thermography was used. This technique is nondestructive and can be performed in realtime during device operation. It has submicrometer spatial resolution and /spl plusmn/1/spl deg/C temperature accuracy. The measured temperatures agree well with the calculated ones. The relationship between the measured temperature and power is almost linear for both types of devices. The junction-to-case thermal resistance of the device fabricated on sapphire substrate is 4.4 times that of the device built on SiC substrate.

A fluxless process of producing tin-rich gold-tin joints in air

A soldering process performed in ambient air without the use of any flux is reported. We believe that this is the first time fluxless soldering process is successfully done in air without prior fluorine treatment. The fluxless process is implemented using Au-Sn binary system. It is based on Au-Sn multilayer design that is substantially tin-rich, namely, with 95 at.% Sn (91.8 wt.% Sn) and 5 at.% Au (8.2 wt.% Au). Over the past 15 years, we have developed numerous fluxless bonding processes. These processes require environments such as H/sub 2/ or N/sub 2/ during the bonding process to inhibit solder oxidation. This requirement is not compatible with the pick-and-place bonding machines widely employed in the industry. Thus, fluxless processing in air has been our lifelong endeavor. After many attempts, we finally achieved some initial success. The bonding process is carried out at 225/spl deg/C. The resulting joints are nearly void-free as confirmed by scanning acoustic microscopy (SAM). To study the microstructure and composition of the samples, scanning electron microscopy (SEM) with energy dispersive X-ray (EDX) spectroscopy was performed on the joint cross-section. The results show that the joint is composed of AuSn/sub 4/ intermetallic grains embedded in a Sn matrix. Re-melting temperatures of the solder joints were measured to range from 214/spl deg/C to 220/spl deg/C, which are consistent with data on the Au-Sn phase diagram.

Thermal modeling and measurement of AlGaN/GaN FETs built on sapphire and SiC substrates

We present thermal modeling and measurement results of AlGaN-GaN heterojunction field effect transistors fabricated on sapphire and SiC substrates, respectively. The device structures are identical except for the substrate material used to grow the AlGaN-GaN heterostructure. One objective is to study the effect of substrate material on the thermal and electrical performance of the resulting devices. To compute the temperature profiles, in-house PAMICE code developed for a three-dimensional structure was used. To measure the temperatures on the chip surface, nematic liquid crystal thermography was used. This technique is nondestructive and can be performed in realtime during device operation. It has submicrometer spatial resolution and /spl plusmn/1/spl deg/C temperature accuracy. The measured temperatures agree well with the calculated ones. The relationship between the measured temperature and power is almost linear for both types of devices. The junction-to-case thermal resistance of the device fabricated on sapphire substrate is 4.4 times that of the device built on SiC substrate.

A fluxless Au-Sn bonding process of tin-rich compositions achieved in ambient air

A new alternative fluxless bonding process conducted in ambient air is reported based on two different Au-Sn multilayer composite designs that are substantially tin-rich; namely, one with composition of 80 at.% Sn (70.54 wt.% Sn) and 20 at.% Au (29.46 wt.% Au), and another with 95 at.% Sn (91.82 wt.% Sn) and 5 at.% Au. (8.18 wt.% Au). We believe that this is the first time that Au-Sn bonding is achieved in air without the use of flux. The bonding process temperatures chosen for constructing 80 Sn-20 Au and 95 Sn-5 Au joints are 285/spl deg/C and 225/spl deg/C, respectively. Once produced, both types of joints were examined using the scanning acoustic microscopy (SAM) to confirm the bonding quality and the results obtained are nearly void-free. To study the microstructure and composition of the samples the scanning electron microscopy (SEM) equipped with energy dispersive X-ray (EDX) detector were conducted across the 95 Sn-5 Au joint cross-section.

Electroplated Sn-Au structures for fabricating fluxless flip-chip Sn-rich solder joints

A fluxless bonding process in hydrogen environment based on newly introduced Sn-Au electroplated multilayer that is highly Sn-rich is presented. Electroplating method is an economical alternative to vacuum deposition method in many soldering applications that require thicker solder joints. Non-eutectic Sn-rich Sn-Au multilayer design with 94 at. % Sn and 6 at. % Au are employed. Microstructure and phase formation of electroplated Sn-Au thin films are investigated using X-ray diffraction method (XRD), Scanning Electron Microscope (SEM), and Energy Dispersive X-ray Spectroscopy (EDX). The joints produced are also examined using these techniques. It is found that the small Sn-Au intermetallic compound (AuSn/sub 4/) grains are uniformly distributed in Sri matrix. Some voids are identified by a Scanning Acoustic Microscope (SAM). The remelting temperature of the joints ranges in 217 /spl sim/ 222/spl deg/C. Highly Sn-rich Sn-Au solder bumps are fabricated by plating through thickness photoresist pattern to develop fluxless flip-chip bonding technique. Thicker bumps (over 50 /spl mu/m) have been produced. This new fluxless bonding process is the first fluxless bonding technology that was successfully achieved by electroplating within authors knowledge.

Hot spot measurement on CMOS-based image sensor using liquid crystal thermograph

CMOS-based (Complementary metal-oxide semiconductor) imager technology offers the opportunity for large scale (1 megapixel and greater) image capture using substantially lower power consumption than conventional imaging sensors such as CCDs (Charge Coupled Device). In addition, CMOS-based image sensors provide the advantages of greater on-chip integration of features and reduced system cost. Such devices are excellent candidates for many consumer imaging applications including digital still cameras, video cameras, and cellular phones with imagers. Typically, any final product using a CMOS-based image sensor will possess myriad additional components each of which may produce heating of the entire system. Increased system temperature arising from dense circuitry can lead to degradation of image quality as the sensor itself heats up. An investigation of the thermal profile of a CMOS image sensor will provide useful information for device design and optimization. In this paper, we present thermographs of CMOS imager sensors produced by a technique using a nematic liquid crystal.