Jeremy Thorpe

Protograph based LDPC codes with minimum distance linearly growing with block size

We propose several LDPC code constructions that simultaneously achieve good threshold and error floor performance. Minimum distance is shown to grow linearly with block size (similar to regular codes of variable degree at least 3) by considering ensemble average weight enumerators. Our constructions are based on projected graph, or protograph, structures that support high-speed decoder implementations. As with irregular ensembles, our constructions are sensitive to the proportion of degree-2 variable nodes. A code with too few such nodes tends to have an iterative decoding threshold that is far from the capacity threshold. A code with too many such nodes tends to not exhibit a minimum distance that grows linearly in block length. In this paper we also show that preceding can be used to lower the threshold of regular LDPC codes. The decoding thresholds of the proposed codes, which have linearly increasing minimum distance in block size, outperform that of regular LDPC codes. Furthermore, a family of low to high rate codes, with thresholds that adhere closely to their respective channel capacity thresholds, is presented. Simulation results for a few example codes show that the proposed codes have low error floors as well as good threshold SNR performance.

Encoders for block-circulant LDPC codes

In this paper, we present two encoding methods for block-circulant LDPC codes. The first is an iterative encoding method based on the erasure decoding algorithm, and the computations required are well organized due to the block-circulant structure of the parity check matrix. The second method uses block-circulant generator matrices, and the encoders are very similar to those for recursive convolutional codes. Some encoders of the second type have been implemented in a small field programmable gate array (FPGA) and operate at 100 Msymbols/second

Methodologies for designing LDPC codes using protographs and circulants

A method is presented for constructing LDPC codes with excellent performance, simple hardware implementation, low encoder complexity, and which can be concisely documented. The simple code structure is achieved by using a base graph, expanded with circulants. The base graph is chosen by computer search using simulated annealing, driven by density evolutions decoding threshold as determined by the reciprocal channel approximation. To build a full parity check matrix, each edge of the base graph is replaced by a circulant permutation, chosen to maximize loop length by using a Viterbi-like algorithm.

Enumerators for protograph ensembles of LDPC codes

This paper considers the problem of finding average enumerators for the class of protograph ensembles, which are related in a certain way to quasi-cyclic codes. Our methods, which are necessarily different from those used to compute enumerators for classical irregular ensembles, can be applied to both codeword and stopping set weight enumerators. The method divides codewords into types based on their partial weight enumerator. For each type, an exponent can be computed for the average number of codewords of that type. Maximizing over types of fixed average weight gives the average enumerator which we seek. Although this maximization step is in general difficult because of non-unique local maxima, we can compute it for simple cases. We show that certain ensembles exist which have a linearly growing minimum distance with high probability, while others have at most sublinearly growing minimum distance with high probability

Memory-efficient decoding of LDPC codes

We present a low-complexity quantization scheme for the implementation of regular (3,6) LDPC codes. The quantization parameters are optimized to maximize the mutual information between the source and the quantized messages. Using this non-uniform quantized belief propagation algorithm, we have simulated that an optimized 3-bit quantizer operates with 0.2 dB implementation loss relative to a floating point decoder, and an optimized 4-bit quantizer operates less than 0.1 dB quantization loss

Constructing LDPC codes from simple loop-free encoding modules

Inspired by recently proposed accumulate-repeat-accumulate (ARA) codes, in this paper we propose a construction method for LDPC codes using simple loop-free encoding modules. Such codes can be viewed as serial/parallel concatenations of simple modules such as accumulators, repetition codes, differentiators, and punctured single parity check codes. Examples are accumulate-repeat-accumulate (ARA) codes, accumulate-repeat-accumulate-accumulate (ARAA) codes and accumulate-repeat-check-accumulate codes, and other variations. These codes constitute a subclass of LDPC codes with very fast encoder structure. They also have a projected graph or protograph representation that allows for high-speed decoder implementation. Based on density evolution, we show through some examples that low iterative decoding thresholds close to the channel capacity limits can be achieved with low maximum variable node degrees, as the block size goes to infinity. The decoding threshold in many examples outperforms that of the best known unstructured irregular LDPC codes constrained to have the same maximum node degree. Furthermore, by puncturing the accumulator modules, any desired higher rate codes can be obtained with thresholds that stay close to their respective channel capacity thresholds uniformly.

A scalable architecture of a structured LDPC decoder

We present a scalable decoding architecture for a certain class of structured LDPC codes. The codes are designed using a small (n, r) protograph that is replicated Z times to produce a decoding graph for a (Z/spl times/n, Z/spl times/r) code. Using this architecture, we have implemented a decoder for a (4096, 2048) LDPC code on a Xilinx Virtex-II 2000 FPGA, and achieved decoding speeds of 31 Mbps with 10 fixed iterations. The implemented message-passing algorithm uses an optimized 3-bit nonuniform quantizer that allows near floating point performance in the waterfall region, with drastically smaller hardware implementation requirements.

Accumulate-repeat-accumulate-accumulate-codes

Inspired by recently proposed accumulate-repeat-accumulate (ARA) codes (Abbasfar et al. (2004)), in this paper we propose a channel coding scheme called accumulate-repeat-accumulate-accumulate (ARAA) codes. These codes can he seen as serial turbo-like codes or as a subclass of low density parity check (LDPC) codes, and they have a projected graph or protograph representation, this allows for a high-speed iterative decoder implementation using belief propagation. An ARAA code can be viewed as a precoded repeat-and-accumulate (RA) code with puncturing in concatenation with another accumulator, where simply an accumulator is chosen as the precoder; thus ARAA codes have a very fast encoder structure. Using density evolution on their associated protographs, we find examples of rate-1/2 ARAA codes with maximum variable node degree 4 for which a minimum bit-SNR as low as 0.21 dB from the channel capacity limit can be achieved as the block size goes to infinity. Such a low threshold cannot be achieved by RA or irregular RA (IRA) or unstructured irregular LDPC codes with the same constraint on the maximum variable node degree. Furthermore by puncturing the accumulators we can construct families of higher rate ARAA codes with thresholds that stay close to their respective channel capacity thresholds uniformly. Iterative decoding simulation results show comparable performance with the best-known LDPC codes but with very low error floor even at moderate block sizes.

The Mastermind game and the rigidity of the Hamming space

A new approach to investigating the Mastermind game and related problems, among them uniquely decodable codes for noiseless adder channel, based on ideas and methods of coding theory is proposed. This approach leads to improved bounds in various problems associated with the rigidity of Hamming spaces.