Jerry C. Kao

A resonant-clock 200MHz ARM926EJ-S TM microcontroller

An ARM926EJ-STM microcontroller with a fully resonant clock distribution network and 16KB data and instruction caches has been implemented in 130nm bulk silicon. Workloads execute successfully across process and temperature corners, and at room temperature, typical-process chips run at clock speeds up to 200MHz with 1.2V supply. At resonance, the microcontroller core dissipates 0.23mW/MHz, recovering 85% of the energy in its clock distribution network. Total power savings range from 20% to 35%, depending on application workload and computation profile.

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic

This paper presents a 14-tap 8-bit finite impulse response (FIR) test-chip that has been designed using a novel charge-recovery logic family, called Enhanced Boost Logic (EBL), to achieve high-speed and low-power operation. Compared to previous charge-recovery circuitry, EBL achieves increased gate overdrive, resulting in low latency overhead over static CMOS design. The EBL-based FIR has been designed with only 1.5 cycles of additional latency over its static CMOS counterpart, while consuming 21% less energy per cycle, based on post-layout simulations of the two designs. The test-chip has been fabricated in a 0.13 μ m CMOS process with a fully-integrated 3 nH inductor. Correct function has been validated in the 365-600 MHz range. At its resonant frequency of 466 MHz, the test-chip dissipates 39.1 mW with a 93.6 nW/MHz/Tap/InBit/CoeffBit figure of merit, recovering 45% of the energy supplied to it every cycle.

RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator

In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.

A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution

A 65nm CMOS 5.5GS/s non-interleaved 5-bit flash ADC with resonant clocking is presented. An on-chip 0.77nH inductor resonates the entire clock distribution network to achieve energy-efficient operation. The ADC occupies 0.035mm2 and consumes 28mW when operating at 5.5GHz, yielding 396fJ per conversion step. The clock network dissipates only 10.7% of total power, consuming 54% lower energy over CV2. By comparison, in a typical flash ADC design, 30% of total power is clock-related. From measurement results, ENOB is 4.56b and 4.11b with fin at 440MHz and 2.04GHz, respectively.

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead

We present a 14-tap 8-bit FIR chip designed using a novel charge-recovery logic family with only 1.5 cycles of additional latency over the best possible static CMOS design. Fabricated in a 0.13µm CMOS process, the chip operates in the 365—600MHz range with a 3nH on-chip inductor. At its resonant frequency of 466MHz, it dissipates 39.1mW and recovers 45% of the energy supplied to it.

A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches

In this paper, we present the design and experimental validation of RF1, a 0.8-1.2GHz frequency-scalable, resonant-clocked FIR filter test-chip with level-sensitive latches. Designed using a fully automated ASIC flow, RF1 was fabricated in a 0.13mum CMOS process with an on-chip inductor and clock generator. At its resonant frequency of 1.03GHz, RF1 dissipates 132mW, with clock power accounting for only 10.8% of total power dissipation. Resonating 42pF of clock load, RF1 achieves 76% clock-power efficiency over CV2 f.