Jessie C. Rosenberg

A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

A 25 Gbps silicon microring modulator based on an interleaved junction.

A silicon microring modulator utilizing an interleaved p-n junction phase shifter with a V(π)L of 0.76 V-cm and a minimum off-resonance insertion loss of less than 0.2 dB is demonstrated. The modulator operates at 25 Gbps at a drive voltage of 1.6 V and 2-3 dB excess optical insertion loss, conditions which correspond to a power consumption of 471 fJ/bit. Eye diagrams are characterized at up to 40 Gbps, and transmission is demonstrated across more than 10 km of single-mode fiber with minimal signal degradation.

Demonstration of a High Extinction Ratio Monolithic CMOS Integrated Nanophotonic Transmitter and 16 Gb/s Optical Link

We present a 16-Gb/s transmitter composed of a stacked voltage-mode CMOS driver and periodic-loaded reverse biased pn junction Mach-Zehnder modulator. The transmitter shows 9-dB extinction ratio and 10.3-pJ/bit power consumption and operates with 1.3 μm light. Penalties as low as 0.5 dB were seen as compared to a 25-Gb/s LiNbO3 transmitter with both a monolithic metal-semiconductor-metal receiver and a reference receiver at 16-Gb/s operation. We also present an analytic expression for relative transmitter penalty (RTP), which allows one to quickly assess the system impact of design parameters such as peak-to-peak modulator drive voltage, modulator figure of merit, and transmitter extinction ratio to determine the circumstances under which a stacked CMOS cascode driver is desirable.

Ultra-low-voltage micro-ring modulator integrated with a CMOS feed-forward equalization driver

We present an all-CMOS micro-ring modulator packaged with a feed-forward equalization driver circuit, operating in charge-injection mode at 8 Gbps with a drive voltage of only 50 mVp-p and a power consumption of 1.8 pJ/bit.

Demonstration of Error-Free 32-Gb/s Operation From Monolithic CMOS Nanophotonic Transmitters

We present a monolithic CMOS-integrated nanophotonic transmitter with a link sensitivity comparable with a 25-Gb/s commercial reference transmitter. Our CMOS transmitter shows error-free operation up to 32 Gb/s, and exhibits a 4.8-dB extinction ratio and 4.9-dB insertion loss at 25 Gb/s.

An integrated silicon photonics technology for O-band datacom

A manufacturable platform of CMOS, RF and opto-electronic devices fully PDK enabled to demonstrate a 4×25 Gb/s reference design is presented. With self-aligned fiber attach, this technology enables low-cost O-band data-com transceivers. In addition, this technology can offer enhanced performance and yield in hybrid-assembly for applications at 25 Gbaud and beyond.

Monolithic Travelling-Wave Mach-Zehnder Transmitter with High-Swing Stacked CMOS Driver

We present a 20 Gb/s monolithically integrated transmitter with stacked CMOS driver and periodic-loaded PN-junction Mach-Zehnder modulator fabricated in IBMs sub-100nm technology node. Transmitter extinction ratios of 10 dB at 20 Gb/s are demonstrated.

A linear push-pull silicon optical modulator

We present a linear push-pull driven silicon modulator fabricated in IBM’s CMOS9WG technology node. The Si modulator shows third order nonlinearity suppression 3 dB superior in comparison with a commercial lithium niobate modulator.

Silicon photonics and challenges for fabrication

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

High-speed and low-power microring modulators for silicon photonics

Microring-based silicon electro-optic modulators allow high-speed and low-power devices to be fabricated in small footprints. A 30 Gbps reverse-biased microring modulator, and an 8 Gbps forward-biased microring modulator with hybrid-integrated preemphasis driver, are presented.