Jesus Grajal

Pipelined Radix-

The appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) FFT architectures. In feedforward architectures radix-2k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

2^{k}

This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency. The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the decimation in time (DIT) and decimation in frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2. Finally, as in previous works, when calculating the RFFT the output samples are obtained in a scrambled order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed.

Feedforward FFT Architectures

A digital channelized receiver is presented for the interception of a wide variety of signals of complex structure, including those with low probability of interception. The receiver is designed from the perspective of the time-frequency analysis. It uses an extended time-frequency representation based on the noncoherent integration of the short-time Fourier transform (STFT) on which the detection system and the encoder work. The encoder includes robust frequency estimation, automatic modulation recognition, and clustering, to handle broadband and simultaneous signals and to prevent out-of-channel detections (a typical phenomenon in channelized receivers). The receiver has been evaluated for a wide range of signals and shows a good performance in terms of detection, estimation, and processing of simultaneous signals. Signals collected from real-life systems and synthetic signals have been utilized.

A Pipelined FFT Architecture for Real-Valued Signals

An algorithm to detect and estimate a linear mixture of deterministic signals corrupted by white Gaussian noise is presented. The number of signals is assumed to be unknown, and the noise power can be either known or unknown. The algorithm is based on an information-theoretic criterion in which the probability of false alarm can be adjusted; typical information criteria, such as the Akaike (AIC) and the minimum description length (MDL) criteria, can be regarded as particular cases of it for given probabilities of false alarm. The proposed approach includes the use of the atomic decomposition and the expectation maximization (EM) algorithms to efficiently approximate the signal maximum likelihood estimate. For the first time, upper-bounds for the probabilities of underestimation and overestimation of the number of signals are obtained. In addition, the constant false-alarm rate (CFAR) characteristic is shown, and the statistical efficiency of the signal parameter estimation is discussed and illustrated by simulation. Numerical experiments show the suitability of the algorithm for signal interception by using synthetic and real-life radar signals.

Digital channelized receiver based on time-frequency analysis for signal interception

This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.

Multiple signal detection and estimation using atomic decomposition and EM

The detection and tracking of an unknown number of targets using a Bayesian hierarchical model with target labels is presented. To approximate the posterior probability density function (PDF), we develop a two-layer particle filter (PF). One deals with track initiation, and the other deals with track maintenance. In addition the parallel partition (PP) method is proposed to sample the states of the surviving targets.

Implementing FFT-based digital channelized receivers on FPGA platforms

This paper deals with the problem of tracking using a sensor network when the sensors are not synchronised. We propose a new algorithm called the asynchronous particle filter that, with much less computational burden than the traditional particle filter, has a slightly poorer performance. Thus, it is a good solution to real-time applications with non-synchronised sensors when high performance is required. The low computational burden of the method lies in the fact that we do not predict and update the state every time a measurement is collected. Its high performance is due to the fact that we account for the time instant at which each measurement was taken.

Two-Layer Particle Filter for Multiple Target Detection and Tracking

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2k , radix-4, and radix-8.

Asynchronous particle filter for tracking using non-synchronous sensor networks

In this paper, we explore the promising capabilities of atomic decomposition (AD) for radar-related applications from a practical point of view. Some enhancements and new approaches are proposed herein, and their implementations are fully detailed. We apply the AD algorithms in two different environments, for signal detection where high sensitivity is the main requirement, and for inverse synthetic aperture radar (ISAR) imaging where focused images, target feature extraction, and computational burden are the fundamental concerns.

Optimum Circuits for Bit Reversal

A new memoryless CORDIC algorithm for the FFT computation is proposed in this paper. This approach calculates the direction of the micro-rotations from the control counter of the FFT, so the area of the rotator hardly depends on the number of rotations, which is particularly suitable for the computation of FFTs of a high number of points. Moreover, the new CORDIC presents other advantages such as the simplification of the basic CORDIC processor used to calculate the micro-rotations, or an easy way to compensate the intrinsic gain of the CORDIC algorithm. Additionally, the VLSI implementation of the algorithm is a pipeline architecture with high performance in terms of speed, throughput and latency.