Jhih-Rong Gao

Design for Manufacturing With Emerging Nanolithography

In this paper, we survey key design for manufacturing issues for extreme scaling with emerging nanolithography technologies, including double/multiple patterning lithography, extreme ultraviolet lithography, and electron-beam lithography. These nanolithography and nanopatterning technologies have different manufacturing processes and their unique challenges to very large scale integration (VLSI) physical design, mask synthesis, and so on. It is essential to have close VLSI design and underlying process technology co-optimization to achieve high product quality (power/performance, etc.) and yield while making future scaling cost-effective and worthwhile. Recent results and examples will be discussed to show the enablement and effectiveness of such design and process integration, including lithography model/analysis, mask synthesis, and lithography friendly physical design.

A new global router for modern designs

In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhance our global router. These techniques include (1) a history based cost function which helps to distribute overflow during iterative rip-ups and reroutes, (2) an adaptive multi-source multi-sink maze routing method to improve the wirelength of maze routing, (3) a congested region identification method to specify the order for nets to be ripped up and rerouted, and (4) a refinement process to further reduce overflow when iterative history based rip-ups and reroutes reach bottleneck. Compared with two state-of-the-art works on ISPD98 benchmarks, NTHU-Route outperforms them in both overflow and wirelength. For the much larger designs from the ISPD07 benchmark suite, our solution quality is better than or comparable to the best results reported in the ISPD07 routing contest.

Flexible self-aligned double patterning aware detailed routing with prescribed layout planning

Self-aligned double patterning (SADP) is a promising manufacturing option for sub-22nm technology nodes. Studies have shown that SADP provides better overlay control than traditional litho-etch-litho-etch double patterning. However, the use of stitch is not allowed, which makes layout decomposition for SADP more difficult. It is necessary to find a new solution to handle pattern conflicts and consider SADP in earlier stages. In this paper, we propose a novel multi-layer SADP-aware detailed routing with prescribed layout planning. Our method is based on a correct-by-construction approach to take SADP compliancy into account during routing, and to achieve layout decomposition simultaneously. The experimental result shows that the proposed approach consistently achieves SADP-compliant solutions on both single-layer and multi-layer designs.

Methodology for standard cell compliance and detailed placement for triple patterning lithography

As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition.

A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction

In routing, finding a rectilinear Steiner minimal tree (RSMT) is a fundamental problem. Todays design often contains rectilinear obstacles, like macro cells, IP blocks, and pre-routed nets. Therefore obstacle-avoiding RSMT (OARSMT) construction becomes a very practical problem. In this paper we present a fast and stable algorithm for this problem. We use a partitioning based method and an ant colony optimization based method to construct obstacle-avoiding Steiner minimal tree (OASMT). Besides, two heuristics are proposed to do the rectilinearization and refinement to further improve wirelength. The experimental results show our algorithm achieves the best wirelength results in most of the test cases and the runtime is very small even for the larger cases each of which has both the number of terminals and the number of obstacles more than 100.

NTHU-Route 2.0: A Robust Global Router for Modern Designs

This paper presents a robust global router called NTHU-Route 2.0 that improves the solution quality and runtime of NTHU-Route by the following enhancements: 1) a new history based cost function; 2) new ordering methods for congested region identification and rip-up and reroute; and 3) two implementation techniques. We report convincing experimental results to show the effectiveness of each individual enhancement. With all these enhancements together, NTHU-Route 2.0 solves all ISPD98 benchmarks with very good quality. Moreover, NTHU-Route 2.0 routes 7 of 8 ISPD07 benchmarks and 12 of 16 ISPD08 benchmarks without any overflow. Compared with other state-of-the-art global routers, NTHU-Route 2.0 is able to produce better solution quality and/or run more efficiently.

Dealing with IC manufacturability in extreme scaling

As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), manufacturability challenges are exacerbated. The nanopatterning through the 193nm lithography is being pushed to its limit, through double/triple or more general multiple patterning, while non-conventional lithography technologies such as extreme ultra-violet (EUV), e-beam direct-write (EBDW), and so on, still have grand challenges to be solved for their adoption into IC volume production. This tutorial will provide an overview of key overarching issues in nanometer IC design for manufacturability (DFM) with these emerging lithography technologies, from modeling, mask synthesis, to physical design and beyond.

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system

Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic node. To overcome its throughput limitation, recently the traditional EBL system is extended into MCC system. In this paper, we present E-BLOW, a tool to solve the overlapping aware stencil planning (OSP) problems in MCC system. EBLOW is integrated with several novel speedup techniques, i.e., successive relaxation, dynamic programming and KDTree based clustering, to achieve a good performance in terms of runtime and solution quality. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both conventional EBL system and MCC system.

Triple patterning lithography (TPL) layout decomposition using end-cutting

Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and end- cut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the con ict number and the stitch number.

Accurate lithography hotspot detection based on principal component analysis-support vector machine classifier with hierarchical data clustering

Abstract. As technology nodes continue to shrink, layout patterns become more sensitive to lithography processes, resulting in lithography hotspots that need to be identified and eliminated during physical verification. We propose an accurate hotspot detection approach based on principal component analysis-support vector machine classifier. Several techniques, including hierarchical data clustering, data balancing, and multilevel training, are provided to enhance the performance of the proposed approach. Our approach is accurate and more efficient than conventional time-consuming lithography simulation and provides a high flexibility for adapting to new lithography processes and rules.