Ji-Hyun Hur

180nm gate length amorphous InGaZnO thin film transistor for high density image sensor applications

In this article, we propose a novel hybrid complementary metal oxide semiconductor (CMOS) image sensor architecture utilizing nanometer scale amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFT) combined with a conventional Si photo diode. This approach will overcome the loss of quantum efficiency and image quality due to the downscaling of the photodiode. The 180nm gate length a-IGZO TFT exhibits remarkable short channel device performance including a low 1/ƒ noise and a high output gain, despite fabrication temperatures as low as 200°C. The excellent device performance has been achieved by a double layer gate dielectric (Al2O3/SiO2) and a trapezoidal active region formed by a tailored etching process. A self aligned top gate structure was employed for low parasitic capacitance. 3D process simulation tools were applied to optimize a four pixel CMOS image sensor structure. The results demonstrate how our stacked hybrid device approach contributes to new device strategies in image sensor architectures. We expect that this approach is applicable to numerous devices and systems in future micro- and nano-electronics.

Nanometer-Scale Oxide Thin Film Transistor with Potential for High-Density Image Sensor Applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

A plasma-treated chalcogenide switch device for stackable scalable 3D nanoscale memory

Stackable select devices such as the oxide p-n junction diode and the Schottky diode (one-way switch) have been proposed for non-volatile unipolar resistive switching devices; however, bidirectional select devices (or two-way switch) need to be developed for bipolar resistive switching devices. Here we report on a fully stackable switching device that solves several problems including current density, temperature stability, cycling endurance and cycle distribution. We demonstrate that the threshold switching device based on As-Ge-Te-Si material significantly improves cycling endurance performance by reactive nitrogen deposition and nitrogen plasma hardening. Formation of the thin Si₃N₄ glass layer by the plasma treatment retards tellurium diffusion during cycling. Scalability of threshold switching devices is measured down to 30 nm scale with extremely fast switching speed of ~2 ns.

Electrical stress-induced instability of amorphous indium-gallium-zinc oxide thin-film transistors under bipolar ac stress

Bipolar ac stress-induced instability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors is comparatively investigated with that under a positive dc gate bias stress. While the positive dc gate bias stress-induced threshold voltage shift (ΔVT) is caused by the charge trapping into the interface/gate dielectric as reported in previous works, the dominant mechanism of the ac stress-induced ΔVT is observed to be due to the increase in the acceptorlike deep states of the density of states (DOS) in the a-IGZO active layer. Furthermore, it is found that the variation of deep states in the DOS makes a parallel shift in the IDS-VGS curve with an insignificant change in the subthreshold slope, as well as the deformation of the CG-VG curves.

First principles study of oxygen vacancy states in monoclinic ZrO2: Interpretation of conduction characteristics

We perform first-principles calculation of monoclinic ZrO2 with oxygen vacancies by using a hybrid functional method to obtain band gap and corresponding energy levels of vacancy states with different charges or coordination numbers. The result agrees well with experimentally measured value. Based on the calculations, explanation for the conduction characteristics which is dependent on applied electric field in monoclinic ZrO2 volume is given.

High performance low voltage amorphous oxide TFT Enhancement/Depletion inverter through uni-/bi-layer channel hybrid integration

A novel amorphous oxide TFT Enhancement/Depletion (E/D) inverter through uni-/bi-layer channel hybrid integration with conventional process is demonstrated. The devices threshold voltages (Vth) is strictly controlled and the fabrication technique is specially designed. Comparing to the reported high speed bootstrapped inverter, the output swing, switching voltage gain and noise margin of E/D inverter are greatly improved and only the ring oscillators speed is slightly degraded while with a small supply voltage of 5V.

Theoretical studies on distribution of resistances in multilevel bipolar oxide resistive memory by Monte Carlo method

We simulate resistance distributions of multilevel oxide bipolar resistive random access memories (ReRAMs) through a physical model with Monte Carlo method. The model is used to explain frequently noticed proportionality relationship between distributions of resistances and multi-levels program voltages. By comparing with the experimental results obtained with TaOx/Ta2O5 bipolar ReRAM, the model is verified to have a good consistency with experiments not only qualitatively but also quantitatively. We demonstrate that the resistance distributions responses are basically determined by the ion migration barrier in the resistance varying thin oxide layer which means that it is a nearly intrinsic material property.

A Monte Carlo simulation for bipolar resistive memory switching in large band-gap oxides

A model that describes bilayered bipolar resistive random access memory (BL-ReRAM) switching in oxide with a large band gap is presented. It is shown that, owing to the large energy barrier between the electrode and thin oxide layer, the electronic conduction is dominated by trap-assisted tunneling. The model is composed of an atomic oxygen vacancy migration model and an electronic tunneling conduction model. We also show experimentally observed three-resistance-level switching in Ru/ZrO2/TaOx BL-ReRAM that can be explained by the two types of traps, i.e., shallow and deep traps in ZrO2.

Magnetic properties of the sendust/Ta2O5 multilayer thin films

The Sendust multilayer thin films were fabricated to improve magnetic properties by rf magnetron sputtering. The effective permeability of the film with 50 A of a Ta2O5 middle layer was 1800 when annealed at 500° C. The coercivity of the film was 0.5 Oe. When the middle‐layer thickness was thicker than 100 A, the result showed no magnetic improvement in permeability and coercivity.