Jian-Jia Chen

Energy-Efficient Scheduling for Real-Time Systems on Dynamic Voltage Scaling (DVS) Platforms

Energy-efficient designs have played import roles for hardware and software implementations for a decade. With the advanced technology of VLSI circuit designs, energy-efficiency can be achieved by adopting the dynamic voltage scaling (DVS) technique. In this paper, we survey the studies for energy-efficient scheduling in real-time systems on DVS platforms to cover both theoretical and practical issues.

Leakage-Aware Energy-Efficient Scheduling of Real-Time Tasks in Multiprocessor Systems

This work targets energy-efficient scheduling of periodic real-time tasks over multiple DVS processors with the considerations of power consumption due to leakage current. A polynomial-time algorithm with a 1.283 approximation bound is proposed when the overheads in turning on/off a processor are negligible. When the overheads are non-negligible, we develop polynomial-time algorithms with a 2 approximation bound. A series of simulation experiments was done for the performance evaluation of the proposed algorithms. The simulation results show that the proposed algorithms could derive schedules very close to optimal solutions.

Worst case delay analysis for memory interference in multicore systems

Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a tasks WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core.

An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor

In the recent decade, voltage scaling has become an attractive feature for many system component designs. In this paper we consider energy-efficient real-time task scheduling over a chip multiprocessor architecture. The objective is to schedule a set of frame-based tasks with the minimum energy consumption, where all tasks are ready at time 0 and share a common deadline. We show that such a minimization problem is NP-hard and then propose a 2.371-approximation algorithm. The strength of the proposed algorithm was demonstrated by a series of simulations, for which near optimal results were obtained.

Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems

Many computing systems have adopted the dynamic voltage scaling (DVS) technique to reduce energy consumption by slowing down operation speed. However, The longer a job executes, the more energy in leakage current the processor consumes for the job. To reduce the power/energy consumption from the leakage current, a processor can enter the dormant mode. Existing research results for leakage-aware DVS scheduling perform procrastination of real-time jobs greedily so that the idle time can be aggregated as long as possible to turn off the processor. This paper proposes algorithms for the procrastination determination of periodic real-time tasks in uniprocessor systems. Instead of greedy procrastination, the procrastination procedures are applied only when the evaluated energy consumption is less than not procrastination. Evaluation results show that our proposed algorithms could derive energy-efficient solutions and outperform existing algorithms. Keywords: Energy-aware systems. .Scheduling, Leakage-aware scheduling. Dynamic voltage scaling. Job procrastination.

Multiprocessor energy-efficient scheduling with task migration considerations

This paper targets energy-efficient scheduling of tasks over multiple processors, where tasks share a common deadline. Distinct from many research results on heuristics-based energy-efficient scheduling, we propose approximation algorithms with different approximation bounds for processors with/without constraints on the maximum processor speed, where no task migration is allowed. When there is no constraint on processor speeds, we propose an approximation algorithm for two-processor scheduling to provide trade-offs among the specified error, the running time, the approximation ratio, and the memory space complexity. An approximation algorithm with a 1.13-approximation ratio for M-processor systems is also derived (M > 2). When there is an upper bound on processor speeds, an artificial-bound approach is taken to minimize the energy consumption with a 1.13-approximation ratio. An optimal scheduling algorithm is then proposed in the minimization of the energy consumption when task migration is allowed.

Proactive Speed Scheduling for Real-Time Tasks under Thermal Constraints

Thermal management becomes a prominent issue in system design for both server systems and embedded systems. A system could fail if the peak temperature exceeds its thermal constraint. This research studies thermal-constrained scheduling for frame-based real-time tasks on a dynamic voltage/speed scaling system. Our objective is to design speed schedulers for real-time tasks by utilizing dynamic voltage/speed scaling to meet both timing and thermal constraints. Two approaches are proposed: One is based on the minimization of the response time under the thermal constraint, and the other is based on the minimization of the temperature under the timing constraint. We present detailed schedulability analysis for both proposed approaches. Our data show that our proposed proactive approaches outperform existing reactive ones.

Multiprocessor energy-efficient scheduling for real-time tasks with different power characteristics

In the past decades, a number of research results have been reported for energy-efficient scheduling over uniprocessor and multiprocessor environments. Different from many of the past results on the assumption for task power characteristics, we consider real-time scheduling of tasks with different power characteristics. The objective is to minimize the energy consumption of task executions under the given deadline constraint. When tasks have a common deadline and are ready at time 0, we propose an optimal real-time task scheduling algorithm for multiprocessor environments with the allowance of task migration. When no task migration is allowed, a 1.412-approximation algorithm for task scheduling is proposed for different settings of power characteristics. The performance of the approximation algorithm was evaluated by an extensive set of experiments, where excellent results were reported.

Timing Analysis for TDMA Arbitration in Resource Sharing Systems

Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. However, performance boosting is constrained by shared resources, such as buses, main memory, DMA, etc.This paper analyzes the worst-case completion (response) time for real-time tasks when time division multiple access (TDMA) policies are applied for resource arbitration.Real-time tasks execute periodically on a processing element and are constituted by sequential superblocks. A superblock is characterized by its accesses to a shared resource and its computation time. We explore three models of accessing shared resources: (1)dedicated access model, in which accesses happen only at the beginning and the end of a superblock, (2) general access model, in which accesses could happen anytime during the execution of a superblock, and (3) hybrid access model, which combines the dedicated and general access models. We present a framework to analyze the worst-case completion time of real-time tasks (superblocks) under these three access models, for a given TDMA arbiter. We compare the timing analysis of the three proposed models for a real-world application.

Energy-Efficient Real-Time Task Scheduling for a DVS System with a Non-DVS Processing Element

Multiple processing elements are often adopted in the current designs of embedded systems. Such configurations impose challenges on hardware/software co-designs with energy-efficient considerations. This paper targets energy-efficient real-time task scheduling of such popular configurations, in which systems are equipped with a DVS processor and a non-DVS processing element (PE). We consider task scheduling under different power consumption models of the non-DVS PE. When the power consumption of the non-DVS PE is independent on the assigned workload, a fully polynomial-time approximation scheme is developed for energy-efficient scheduling. When the energy consumption of the non-DVS PE depends on the assigned workload, a 0.5-approximation algorithm is developed to maximize the energy saving, compared to the execution of tasks on a DVS processor. Extensive simulations were performed to evaluate the capability of our proposed algorithms. The results show that our algorithms are very effective in energy-efficiency