Jiang-Kai Zuo

Low-Leakage SMARTMOS 10W Technology At 0.13μm Node with Optimized Analog, Power and Logic Devices for SOC Design

SMARTMOS 10 W technology, which was developed based on 0.13-micron technology node, combines optimized power, analog and digital devices for wireless and consumer applications. As compared to the current state-of-the-art technologies, significant size shrink in power devices is achieved for cost reduction while the leakage is lowered by more than 20 times to minimize power consumption. Also, the technology doubles the performance of analog matching across FETs, resistors and capacitors. This technology is an excellent fit for all portable applications in which device size, battery life, sound quality and overall integration capability are key considerations.

Approach to the silicon limit: Advanced NLDMOS in 0.13 μm SOI technology for automotive and industrial applications up to 110V

We report our development of a novel NLDMOS in SOI based smart power technology, integrated into Freescales 0.13μm CMOS platform. The new NLDMOS not only achieves BVDSS up to 140V in both low side and high side operations, but more importantly, the Rdson*Area is able to shrink at least 35-40% below the current benchmark, which is the lowest reported for BVDSS ranging from 50V to 138V. For the first time, we demonstrated LDMOS devices which approach the Si limit. The devices also achieve very competitive performance in both SOA and the reliability tests under HCI stress as well as high temperature reverse bias (HTRB) stress.