Jianhui Jiang

A Method of Gate-Level Circuit Reliability Estimation Based on Iterative PTM Model

The rapid development of nanotechnology has opened up new possibilities and introduced new challenges for circuit design. It is very important to study new analysis methods for accurate circuit reliability. Few methods for evaluating circuit reliability were proposed in recent years. For example, the original probabilistic transfer matrix (PTM) model has large time and space overhead, so it can only calculate small scale circuits, the improved PTM model proposed in [2] can handle large scale circuits but it also has large time overhead. In this paper, the concept of macro-gate is defined and an iterative PTM model based on macro-gate is proposed. Based on this model, a circuit reliability evaluation algorithm that can calculate the circuit reliability from primary input to any level of the circuit is given. The complexity of the proposed algorithm related to the number of macro-gates contained in the circuit is linear. Experimental results show that the proposed method has the same accuracy as the PTM model, but it has lower time overhead for large circuits.

Fault Injection Scheme for Embedded Systems at Machine Code Level and Verification

In order to evaluate software from the third party whose source codes are not available, after a careful analysis of the statistic data sorted by Orthogonal Defect Classification, and the corresponding relation between patterns of high level language programs and machine codes, we propose a fault injection scheme at machine code level suitable respectively to the IA32 ARM and MIPS architecture, which takes advantage of mutating machine code. To prove the feasibility and validity of this scheme, two sets of programs are chosen as our experimental target: Set I consists of two different versions of triangle testing algorithms, and Set II is a subset of the Mibench which is a collection of performance benchmark programs designed for embedded systems; we inject both high level faults into the source code written in C language and the corresponding machine code level faults directly into the executables, and monitor their running on Linux. The results from experiments show that at least 96% of total similarity degree is obtained. Therefore, we conclude that the effect of injecting corresponding faults on both the source code level and machine code level are mostly the same. Therefore, our scheme is rather useful in analyzing system behavior under faults.

A PIN-Based Dynamic Software Fault Injection System

Fault injection plays a critical role in the verification of fault-tolerant mechanism, software testing and dependability benchmarking for computer systems. In this paper, according to the characteristics of software faults, we propose a new fault injection design pattern based on the PIN framework provided by Intel company, and develop a PIN-based dynamic software fault injection system (PDSFIS). Faults can be injected by PDSFIS without the source code of target applications under assessment, nor does the injection process involve interruption or software traps. Experimental assessment results of an Apache Web server obtained by the dependability benchmarking are presented to demonstrate the potentials of PDSFIS.

A Safe Measurement-Based Worst-Case Execution Time Estimation Using Automatic Test-Data Generation

This paper proposes a new safe measurement-based estimation method for Worst-Case Execution Time (WCET) of programs in real-time systems. The latest progress in Pattern Recognition of learning to detect unseen object classes by between-class attribute transfer has been used for automatic test-data generation in our method. Based on control flow graph partition, execution profiles of each basic block and probabilities of their executions can be extracted during program executions driven by test data. Afterwards, a critical path can be identified by calculating its execution probability among all feasible paths. With measurement for critical paths, WCET can be obtained by adding static analysis of hardware features to measurement results. The objective of this paper is not to present finished or almost finished work. Instead we hope to trigger discussion and solicit feedback from the community in order to avoid pitfalls experienced by others and to help focus our research.

A New Method for Test Suite Reduction

Test suite reduction is to find a subset of the test suite containing a minimal number of test cases that can satisfy all test requirements. Test suite reduction techniques attempt to remove redundant test cases. Existed minimal set selection methods cannot guarantee the optimality of representative sets obtained. This paper adapts the Quine-McCluskey algorithm to find the minimal representative set. To demonstrate the applicability of the approach, we conduct an experimental comparison. The results show that the Quine-McCluskey approach can identify the optimal test suite. Meanwhile, the application of this method for testing the automatic fare collection systems of Shanghai Metro also validated that it is effective.

Fault-tolerant systems with concurrent error-locating capability

Fault-tolerant systems have found wide applications in military, industrial and commercial areas. Most of these systems are constructed by multiple-modular redundancy or error control coding techniques. They need some fault-tolerant specific components (such as voter, switcher, encoder, or decoder) to implement error-detecting or error-correcting functions. However, the problem of error detection, location or correction for fault-tolerance specific components themselves has not been solved properly so far. Thus, the dependability of a whole fault-tolerant system will be greatly affected. This paper presents a theory of robust fault-masking digital circuits for characterizing fault-tolerant systems with the ability of concurrent error location and a new scheme of dual-modular redundant systems with partially robust fault-masking property. A basic robust fault-masking circuit is composed of a basic functional circuit and an error-locating corrector. Such a circuit not only has the ability of concurrent error correction, but also has the ability of concurrent error location. According to this circuit model, for a partially robust fault-masking dual-modular redundant system, two redundant modules based on alternating-complementary logic consist of the basic functional circuit. An error-correction specific circuit named as alternating-complementary corrector is used as the error-locating corrector. The performance (such as hardware complexity, time delay) of the scheme is analyzed.

A novel NMR structure with concurrent output error location capability

This paper proposes a novel N-modular redundancy (NMR) structure with concurrent output error location (COEL) capability. The concurrent output error locatable NMR structure consists of a conventional NMR structure and a totally self-checking (TSC) extra circuit with N+1 two-rail code outputs. This extra circuit is used for locating the output error produced by any replicated module or the voter, and the internal fault produced by the extra circuit itself. Such a self-checking extra circuit is called the output error locator (OEL). It is constructed by conventional TSC two-rail code checkers (TRCs) and self-testing multi-input comparators. Each comparator is made by adding one extra two-rail code input to the cascaded multi-input comparator. The error handling capabilities, hardware complexity and propagation delay are analyzed for the proposed OEL. The performance of the proposed scheme and that of the Gaitaniss scheme are compared for a triple modular redundancy (TMR) structure.

A Worst-case execution time analysis approach based on independent paths for ARM programs

To overcome disadvantages of traditional worst-case execution time (WCET) analysis approaches, we propose a new WCET analysis approach based on independent paths for ARM programs. Based on the results of program flow analysis, it reduces and partitions the control flow graph of the program and obtains a directed graph. Using linear combinations of independent paths of the directed graph, a set of feasible paths can be generated that gives complete coverage in terms of the program paths considered. Their timing measurements and execution counts of program segments are derived from a limited number of measurements of an instrumented version of the program. After the timing measurement of the feasible paths are linearly expressed by the execution times of program segments, a system of equations is derived as a constraint problem, from which we can obtain the execution times of program segments. By assigning the execution times of program segments to weights of edges in the directed graph, the WCET estimate can be calculated on the basis of graph-theoretical techniques. Comparing our WCET estimate with the WCET measurement obtained by the exhaustive measurement, the maximum error ratio is only 8.259 3 %. It is shown that the proposed approach is an effective way to obtain the safe and tight WCET estimate for ARM programs.

A Study on Software Reliability Prediction Based on Transduction Inference

Non-parametric statistical methods are applied to verdict that early failure behavior of the testing process may have less impact on later failure process, so it happens in software failure time prediction that one does not have enough information to estimate the software failure process well but do have enough information to estimate the failure data at given instance. The prediction accuracy of software reliability prediction models based on recurrent neural network, feed-forward neural network, relevance vector machine, support vector machine and some nonhomogeneous Poisson process models is compared. Experimental results show that software failure time prediction models based on transduction inference theory could achieve higher prediction accuracy.

Sequential Frequency Vector Based System Call Anomaly Detection

Although either of temporal ordering and frequency distribution information embedded in process traces can profile normal process behaviors, but none of ever published schemes uses both of them to detect system call anomaly. This paper claims combining those two kinds of useful information can improve detection performance and firstly proposes sequential frequency vector (SFV) to exploit both temporal ordering and frequency information for system call anomaly detection. Extensive experiments on DARPA-1998 and UNM dataset have substantiated the claim. It is shown that SFV contains richer information and significantly outperforms other techniques in achieving lower false positive rates at 100% detection rate.