Jianmin Cao

A new stretched-exponential model for NBTI effects in pMOSFETs

Negative bias temperature instability (NBTI) has greatly limited the lifetimes for product lifetime. Traditional degradation models, such as the classic reaction-diffusion (R-D) model, stretched-exponential (S-E) model and R-D saturated model, have been proposed to quantitatively describe it. In this paper, we use both analytical formulations as well as numerical solutions to explore the relations among these models. In addition, we propose a new S-E model for H2 diffusion. Compared to the previous S-E model, our proposed S-E model, with high accuracy approximation to the R-D model, can be used to explain the NBTI saturation and lower degradation exponent, and is more suitable for the applications of integrated circuit simulation and analysis.

Investigation of single-event transient mitigation via pulse quenching in logic circuits

A layout technique which can mitigate single-event effect via pulse quenching is tested in this paper. The new limitation of application of this layout technique is affirmed in 65nm technology. The layout design via pulse quenching has no effects in PMOS, but it can work in NMOS in basic logical circuits. Combinational logic circuits still can use this method to defense single-event effect.

Characterization of single event transient effects fabricated in triple well CMOS process

This paper presents a novel hardening triple-well design for an six-transistors CMOS memory cell fabricated in 65 nm feature size. The new approach calculates the effects of single event transient (SET) with junction currents, which is derived based on device physics. Simulation presents that charge collection can be effectively mitigated with the use of guard ring contact in triple-well CMOS process. The deposited charge can induce parasitic bipolar amplification to broaden the transient widths between adjacent devices especially for the PMOS under the effects of potential gradient in deep N-well region.

A NBTI inhibition method with channel doping concentration in pMOSFETs

By using the MOS energy band diagram and Negative Bias Temperature Instability (NBTI) degradation model, an equation of NBTI degradation with channel doping concentration has been derived. Meanwhile, a new NBTI inhibition method by using different doping concentration has been proposed. The quantitatively calculation and simulation results show that, with the proposed method, the NBTI inhibition rate can reach 25.6%. The fruit in this research can be used to design integrated circuits and devices with high reliability.

Numerical simulation of DB-NBTI degradation caused by a sheet of interface charge

In this paper, we combine the Reaction-Diffusion Model of Negative Bias Temperature Instability (NBTI) with the two-dimension semiconductor device simulator, and calculate the interfacial charge after extracting the electric field across gate oxide and the hole density at Si/SiO2 interface. A novel non-uniform interface charge distribution model is proposed by taking a sheet of interface charge into account so that the device degradation of drain bias NBTI (DB-NBTI) can be simulated and analyzed. The results show that, as for DB-NBTI, under constant drain bias and part of NBTI interface charge still degrade with the exponent value of 1/6 of the Reaction-Diffusion Model, the degradation of threshold voltage deviates from the traditional power exponent of 1/6. The deviation of degradation curve can be explained by the comparison and analysis of the hole density at the Si/Si02 interface. These results are helpful in pushing DB-NBTI study, and improving the model and methods of its numerical simulation.

Total ionizing dose effects on triple-gate FETs

By radiating different amount of radiation to the pseudo-MOS transistor, the corresponding I-V characterristic curve can be obtained. Additionally, the density of interface traps and the density of trapped-oxide charges which origin from the buried oxide layer of the SOI material while under radiating can be obtained using the middle band voltage analyze method. The analysis of the accumulation of the trap current in the buried oxide layer and the effect of it can be done using these parameters together with the Altal 3D device simulation software.