Jie Liu

Low-Complexity RLS Algorithms Using Dichotomous Coordinate Descent Iterations

In this paper, we derive low-complexity recursive least squares (RLS) adaptive filtering algorithms. We express the RLS problem in terms of auxiliary normal equations with respect to increments of the filter weights and apply this approach to the exponentially weighted and sliding window cases to derive new RLS techniques. For solving the auxiliary equations, line search methods are used. We first consider conjugate gradient iterations with a complexity of operations per sample; being the number of the filter weights. To reduce the complexity and make the algorithms more suitable for finite precision implementation, we propose a new dichotomous coordinate descent (DCD) algorithm and apply it to the auxiliary equations. This results in a transversal RLS adaptive filter with complexity as low as multiplications per sample, which is only slightly higher than the complexity of the least mean squares (LMS) algorithm ( multiplications). Simulations are used to compare the performance of the proposed algorithms against the classical RLS and known advanced adaptive algorithms. Fixed-point FPGA implementation of the proposed DCD-based RLS algorithm is also discussed and results of such implementation are presented.

Architecture and FPGA Design of Dichotomous Coordinate Descent Algorithms

In the areas of signal processing and communications, such as antenna-array beamforming, adaptive filtering, multiuser and multiple-input-multiple-output (MIMO) detection, channel estimation and equalization, echo and interference cancellation, and others, solving linear systems of equations often provides an optimal performance. However, this is also a very complicated operation that designers try to avoid by proposing different suboptimal techniques. The dichotomous coordinate descent (DCD) algorithm allows linear systems of equations to be solved with high computational efficiency. In this paper, we present architectures and field-programmable gate-array (FPGA) designs of two variants of the DCD algorithm, which are known as cyclic and leading DCD algorithms. For each of these techniques, we present serial designs, group-2 and group-4 designs, as well as a design with parallel update of the residual vector for the cyclic DCD algorithm. These designs have different degrees of parallelism, thus enabling a tradeoff between FPGA resources and computation time. The serial designs require the smallest FPGA resources; they are well suited for applications where many parallel solvers are required, e.g., for detection in MIMO-orthogonal-frequency-division-multiplexing communication systems. The parallelism introduced in the proposed group-2 and group-4 designs allows faster convergence to the true solution at the expense of an increase in FPGA resources. The design with parallel update of the residual vector provides the fastest convergence speed; however, if the system size is high, it may result in a significant increase in FPGA resources. The proposed fixed-point designs provide an accuracy performance that is very close to the performance of floating-point counterparts and require significantly lower FPGA resources than techniques based on QR decomposition.

An FPGA-based MVDR Beamformer Using Dichotomous Coordinate Descent Iterations

The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD core. Antenna beampatterns obtained from weights calculated in the fixed-point FPGA platform are compared with those of a floating-point simulation. The comparison shows good match of the results for linear arrays of as large as 64 elements. For a 64-element array, the proposed design could provide a weight update rate as high as 28 kHz.

FPGA Implementation of DCD Based CDMA Multiuser Detector

A field-programmable gate array (FPGA) implementation of a new algorithm for multiuser detection (MUD) is presented in this paper. This FPGA design is based on the dichotomous coordinate descent (DCD) algorithm. The DCD algorithm allows the multiplication-free solution of the normal equations appearing in the MUD problem. This results in an area-efficient FPGA design that requires about 400 slices and offers a constant throughput over a signal-to-noise ratio range. Results obtained from the fixed-point FPGA implementation are compared with those of a floating-point implementation. The bit- error-rate field-programmable gate arrayperformance comparison shows good match of the results for as large number of users as 50.

Fast RLS algorithm using dichotomous coordinate descent iterations

The recursive least squares (RLS) adaptive filtering problem is expressed in terms of auxiliary normal equations with respect to increments of the filter weights. By applying this approach to the exponentially weighted case, a new structure of the RLS algorithm is derived. For solving the auxiliary equations, dichotomous coordinate descent (DCD) iterations with no explicit division and multiplication are used. This results in a transversal RLS adaptive filter with as low complexity as 3N multiplications per sample (N being the filter length), which is only slightly higher than the complexity of the Least Mean Squares (LMS) algorithm (2 AT multiplications). Simulations are used to compare the performance of the proposed algorithm against the classical RLS and known advanced adaptive algorithms. Fixed-point FPGA implementation of the proposed DCD-based RLS algorithm is discussed and results of such implementation are presented.

FPGA implementation of affine projection adaptive filter using coordinate descent iterations

In this paper, we present an FPGA implementation of a low complexity affine projection (AP) adaptive filtering algorithm based on a novel low complexity recursive filtering technique and filter update that is incorporated in dichotomous coordinate descent iterations. This adaptive algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. For the projection order 8 and filter lengths 16 to 512 the design occupies an area smaller than 2900 FPGA slices.

FPGA Implementation of RLS Adaptive Filter Using Dichotomous Coordinate Descent Iterations

In this paper, we present an FPGA implementation of a Recursive Least Squares adaptive filtering algorithm based on dichotomous coordinate descent iterations. The algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. For arbitrary regressors (as in antenna array beamforming), the proposed implementation allows significant increase in the weight update rate compared to implementations based on QR decomposition; for 9 and 32-element arrays, the update rates are as high as 162 kHz and 31 kHz, respectively. For 16-tap and 64-tap transversal filters, the proposed implementation provides the weight update rate 207 kHz and 76 kHz, respectively.

FPGA Design of Box-Constrained MIMO Detector

In this paper, a box-constrained MIMO detector is considered that allows simple FPGA implementation and provides improvement in the detection performance compared to the MMSE detector. The box-constrained detector is implemented using dichotomous coordinate descent iterations. We investigate the design throughput against the BER performance and the design complexity in terms of the number of logic slices. The proposed design requires as few as 637, 658, and 667 slices for 4 × 4, 8 × 8, and 16 × 16 MIMO systems, respectively, which is significantly less than that required by known designs of the MMSE detector.

Dynamically regularized RLS-DCD algorithm and its FPGA implementation

In this paper, we present an FPGA implementation of a dynamically regularized recursive least squares adaptive filtering algorithm based on dichotomous coordinate descent iterations. The algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. The proposed implementation allows significant increase in the weight update rate compared to a implementation based on unregularized QR decomposition; for 16 and 64-element adaptive antenna arrays, the update rate is as high as 176 kHz and 31 kHz, respectively.

DCD-based simplified matrix inversion for MIMO-OFDM

This paper presents a simple approach for matrix inversion by using dichotomous coordinate descent (DCD) algorithm. The idea of the approach is that the DCD algorithm obtains separately the individual columns of the inverse of the matrix. Owing to the low complexity of hardware implementation of the individual DCD algorithm, a block of DCD processors can be adopted to obtain the columns of the inverse of the channel correlation matrix in parallel with reduced hardware occupation.