Jie Zeng

High-Holding-Voltage Silicon-Controlled Rectifier for ESD Applications

Low-voltage-triggering silicon-controlled rectifier (LVTSCR) having a gate structure can offer a low trigger voltage in electrostatic discharge (ESD) applications. To avoid the threat of latch-up, the lateral width of LVTSCR is often stretched to obtain a relatively high holding voltage. The resulting lateral dimension increase, however, enlarges the size of LVTSCR. In this letter, a new method to increase the holding voltage of LVTSCR is developed. It is based on adding a floating-n-well region in the LVTSCR and can increase the holding voltage without requiring additional layout area. Furthermore, with this new LVTSCR, it is possible to implement an ESD protection operation within a very small window of 1 V.

Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device

A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCRs I-V characteristics is analyzed via TCAD simulation results as well.

GGNMOS as ESD protection in different nanometer CMOS process

Grounded-gate NMOS (GGNMOS) plays a more important role in electrostatic discharge (ESD) protection because of its simple structure and low trigger voltage. Various GGNMOS based on 90nm, 65nm and 40nm CMOS process are compared to investigate its ESD characteristic changes with process advancing. Results show that the key parameters, including channel width and length, have great influence on its ESD metrics.

Low-Capacitance SCR Structure for RF I/O Application

Electrostatic discharge (ESD) devices based on diodes and silicon controlled rectifier for RF I/O protection are evaluated on both ESD and RF performance. Varying from the architecture, layout design and metal interconnection, candidate devices show different parasitic capacitance, ESD efficiency, and turn on speed. Potential solution for further RF I/O application is verified.

Lateral IGBT in thin SOI process for high voltage ESD application

A high voltage laterally insulated-gate-bipolar-transistor (LIGBT) built in ultra-thin silicon-on-insulator (SOI) is reported. A theoretical analysis about the efficient approach to increasing the holding voltage of LIGBT starting with BJTs has been proposed. Higher holding voltage and almost the same turn-on speed is achieved by segmenting the emitter area of LIGBT to increase the resistance.

Transient voltage suppressor based on diode-triggered low-voltage silicon controlled rectifier

Transient voltage suppressor (TVS) has been widely used for electronic system ESD protection. A good TVS is usually costive as it needs some special processes and with extra masking layers for fabrication. A novel TVS design based on the standard CMOS process will be much attractive. This work proposes a new TVS device using a CMOS compatible diode-triggered silicon controlled rectifier (DLVTSCR) as the core device. Due to the available of multiple trigger mechanisms and the dual current paths for bypassing the ESD current, the newly proposed device is able to sink an ESD current of over 10 A. In addition, the holding voltage is promoted up to 6.83 V and the trigger voltage is lowered down to 10.8 V which is well suit for most portable device applications.

Minimizing Multiple Triggering Effect in Diode-Triggered Silicon-Controlled Rectifiers for ESD Protection Applications

The diode-triggered silicon-controlled rectifier (DTSCR) is frequently used for low-voltage electrostatic discharge (ESD) protection applications, but such a device can exhibit two snapbacks and consequently can possess an undesirable large trigger voltage. This letter investigates the mechanism underlying the DTSCRs multiple triggering. An improved DTSCR for reducing the second trigger voltage and increasing the ESD safe margin is proposed and verified in a 65-nm complementary metal-oxide-semiconductor process. The improved DTSCRs turn-on characteristic is also discussed.