Jienan Chen

Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System

In this paper, we apply the voltage overscaling (VOS) technique to the residue-number-system (RNS)-based digital signal processing system for achieving high energy efficiency. To mitigate the soft errors caused by VOS, we propose a new method, called joint RNS-RPR (JRR), which is the combination of RNS and the reduced precision redundancy (RPR) technique. The JRR technology inherits the properties of RNS, including shorter critical path, low complexity, and low power. Moreover, JRR can achieve higher power reduction than RNS for VOS applications. Since the soft errors caused by VOS lead to significant performance degradation of RNS, we use the information from RNS and RPR to achieve a high recovering probability of the soft errors with low hardware complexity. From the case study of finite impulse response (FIR) filter design based on the 0.25- μm 2.5-V CMOS technology, we find that JRR can save 62% more energy compared to the traditional FIR with a less than 2-dB signal noise ratio performance loss. We also find that JRR has lower complexity and better performance than the traditional soft error mitigation methods.

Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed-area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18-μm technology are also provided.

Stochastic MIMO Detector Based on the Markov Chain Monte Carlo Algorithm

A stochastic computing framework for a Markov Chain Monte Carlo (MCMC) multiple-input-multiple-output (MIMO) detector is proposed, in which the arithmetic operations are implemented by simple logic structures. Specifically, we introduce two new techniques, namely a sliding window generator (SWG) and a log-likelihood ratio based updating method (LUM), to achieve an efficient design. The SWG utilizes the variance in stochastic computations to increase the transition probability of the MCMC detector, while the LUM reduces the hardware cost. As a case study, we design a fully-parallel stochastic MCMC detector for a 4 ×4 16-QAM MIMO system using 130 nm CMOS technology. The proposed detector achieves a throughput of 1.5 Gbps with only a 0.2 dB performance loss compared to a traditional floating-point detection method. Our design has a 30% better ratio of gate count to scaled throughput compared to other recent MIMO detectors.

Stochastic Iterative MIMO Detection System: Algorithm and Hardware Design

In this paper, we propose a Stochastic iterative multiple-input multiple-output (SIM) detection system based on the Markov chain Monte Carlo (MCMC) method. To improve the detection performance, the Gibbs sampler of the MCMC detector in the SIM is updated by the decoded bits from a channel decoder directly. The channel decoder is part of the updating unit that generates the new samples in the MCMC updating process. We also implement the SIM in a fully parallel scheme, which achieves a high detection speed. As a case study, we have designed and synthesized a 128-parallel 4 × 4 16-QAM SIM system using a CMOS 130 nm technology with a core area of 1.98 mm 2 and 457K logic gates. The SIM detection system can achieve a throughput of 787.5Mbps with a frame error rate (FER) 10-3 at Eb/N0=7dB, equaling the FER of a traditional iterative MIMO detection with four outer iterations.

High Throughput Stochastic Log-MAP Turbo-Decoder Based on Low Bits Computation

In this letter, we propose a high throughput stochastic Low Bits Computation (LBC) turbo decoder. We represent the signal by a 3-bits width stochastic stream, which improves the accuracy of stochastic computation significantly. We have designed and synthesized our design based on CMOS 90 nm technology. The report shows that the proposed decoder can achieve 4.0 Gbps with 7.1 M gate count to decode a 2048-length R=1/3 turbo code, when the bit error rate (BER) is 10-5 @ Eb/N0=1.25 dB.

A novel FIR filter based on stochastic logic

In this paper, we proposed a novel Finite Impulse Response Filter based on stochastic logic referred as SFIR. The proposed SFIR only requires the wire selecting scheme without any logic gate resource. We first map the FIR function to stochastic computation domain. The FIR function is implemented by the wire selecting (WS) method which only requires wire interleaving. Hence the SFIR can achieve ultra high throughput and low cost when apply in the stochastic based system. The SFIR with backward conversion module also has lower hardware cost than traditional method under a given quantization width, which can apply in the low SNR required system and the error tolerant system.

Sparse Code Multiple Access Decoding Based on a Monte Carlo Markov Chain Method

Nonorthogonal multiple access technology has been proposed for use in 5G communications systems. In particular, the sparse code multiple access (SCMA) scheme is believed to be one of the most promising techniques among the various nonorthogonal approaches that have been investigated. In this letter, we focus on reducing the complexity of SCMA decoding and we propose a Monte Carlo Markov Chain (MCMC) based SCMA decoder. Benefiting from the linearly increasing complexity of the MCMC method, the proposed SCMA decoder has only 10% of the computational load compared to previous state-of-the-art methods when the codebook size is 64. Consequently, the MCMC SCMA decoder has great potential for use in practical system implementations.

Low power digital signal processing scheme via stochastic logic protection

In this paper, we proposed a low power digital signal processing (DSP) scheme with stochastic logic protection. The reduction of supply voltage will reduce the power consumption effectively. However, the timing violation will be happened when the voltage overscaling (VOS) is applied. Fortunately, the stochastic logic has simple hardware structure, and the critical path is short. Thus, we can use stochastic logic as the error control (EC) module to mitigate the soft error by the VOS. Compared with traditional EC based low power DSP, the proposed method can achieve higher energy efficiency with high performance. According to the case study of a 26-tap FIR filter, the stochastic logic based EC module can achieve 65% power saving within 2.5dB signal-to-noise ratio (SNR) loss, which outperforms 6dB than traditional RPR method. When the soft error for each logic gate is considered, the advantage of SFIR based system is more obvious than traditional method.

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

In this paper, we design a hardware and energy-efficient stochastic lower-upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the complex arithmetic operations in LUD can be performed with simple logic gates. With proposed dual partition computation method, the stochastic multiplier and divider exhibit high computation accuracy with relative short length stochastic stream. We have designed and synthesized the stochastic LUD with CMOS 130-nm technology. According to the postlayout report, the hardware efficiency of the stochastic LUD is as high as 1.5× compared with the exiting LUD methods, and the energy efficiency is also higher than the state-of-the-art LUD when the matrix dimension is 8 × 8 and larger.

Sliding Window Method for stochastic LDPC decoder

This paper proposes a Sliding Window Method (SWM) for stochastic Low Density Parity Check (LDPC) decoder designing. The SWM is formulated for solving the latch-up problem in the Variable Nodes (VN) information updating. The bit in the latch-up state is evolved from the information bit in the sliding window. Then, an optimized hardware structure is proposed for SWM. Compared with traditional VN structure, the SWM require about 35% less hardware resources to achieve the same BER performance.