Jih-g Shen

Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication

Reconfigurable computing brings immense flexibility to on-chip processing while network-on-chip has improved flexibility in on-chip communication. Integrating these two areas of research reaps the benefits of both and represents the promising future of multiprocessor systems-on-chip. Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication is the one of the first compilations written to demonstrate this future for network -on-chip design. Through dynamic and creative research into questions ranging from integrating reconfigurable computing techniques, to task assigning, scheduling and arrival, to designing an operating system to take advantage of the computing and communication flexibilities brought about by run-time reconfiguration and network-on-chip, this book represents a complete source of the techniques and applications for reconfigurable network-on-chip necessary for understanding of future of this field.

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

We propose a UML-based hardware/software co-design platform for partially reconfigurable systems, targeting mainly at network security systems. Applications with heavy computing are implemented as the partially reconfigurable hardware tasks for enhancing the system performance and flexibility, which means that a network security embedded system can dynamically reconfigure one part of the system at run-time according to different security needs while other parts are still functioning. We further propose a partially reconfigurable hardware template, using which the users only need to integrate their hardware applications with the template without going through the full partial reconfiguration flow. The template has an average overhead of only 0:62% of the total resources in Xilinx Virtex-II XC2V3000 FPGA. Furthermore, our proposed platform includes a UML-based system model that can directly interact with the system hardware architecture. Compared to the synthesis based estimation methods with inaccuracy ranging from -23% to +234% for the execution time of dynamically partially reconfigurable hardware tasks, by using our platform users can directly measure the execution time and use them to validate system correctness and performance at a high-level phase, which significantly reduces the number of iterations in the system development.

Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems

With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such runtime task relocation. In this work, we propose a new Relocatable Hardware-Software Scheduling (RHSS) method that not only can be applied to dynamically relocatable hardware-software tasks, but also increases the reconfigurable hardware resource utilization, reduces the reconfigurable hardware resource fragmentation with realistic placement methods, and makes best efforts at meeting the real-time constraints of tasks. The feasibility of the proposed relocatable hardware-software scheduling algorithm was proved by applying it to some randomly generated examples and a real dynamically reconfigurable network security system example. Compared to the quadratic time complexity of the state-of-the-art Adaptive Hardware-Software Allocation (AHSA) method, RHSS is linear in time complexity, and improves the reconfigurable hardware utilization by as much as 117.8%. The scheduling and placement time and the memory usage are also drastically reduced by as much as 89.5% and 96.4%, respectively.

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip

The set of applications communicating via a Network-on-Chip (NoC) and the NoC itself both have varying run-time requirements on reliability and power-efficiency. To meet these requirements, we propose a novel Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture which allows processing elements, routers, and data encoding methods to be reconfigured at runtime. Further, an intelligent selection of encoding methods is achieved through a REasoning And Learning (REAL) framework at run-time. An instance of PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to a conventional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of a conventional NoC by 71%, 32%, and 277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. Experiments have thus shown that PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption, at the same amount of overheads in performance and hardware usage.

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UML-based hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS cannot only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods.

Network-on-chip router design with buffer-stealing

Communication in a Network-on-Chip (NoC) can be made more efficient by designing faster routers, using larger buffers, larger number of ports and channels, and adaptive routing, all of which incur significant overheads in hardware costs. As a more economic solution, we try to improve communication efficiency without increasing the buffer size. A Buffer-Stealing (BS) mechanism is proposed, which enables the input channels that have insufficient buffer space to utilize at runtime the unused input buffers from other input channels. Implementation results of the proposed BS design for a 64-bit 5-input-buffer router show a reduction of the average packet transmission latency by up to 10.17% and an increase of the average throughput by up to 23.47%, at an overhead of 22% more hardware resources.

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption

The set of applications communicating via a Network-on-Chip (NoC) and the NoC itself both have varying run-time requirements on reliability and power-efficiency. To meet these requirements, we propose a novel Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture which allows processing elements, routers, and data encoding methods to be reconfigured at runtime. Further, an intelligent selection of encoding methods is achieved through a REasoning And Learning (REAL) framework at run-time. An instance of PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to a conventional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of a conventional NoC by 71%, 32%, and 277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. Experiments have thus shown that PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption, at the same amount of overheads in performance and hardware usage.

Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip

Crosstalk interferences and high dynamic power consumption in a network-on-chip (NoC) are two increasingly problematic design issues. Using data codecs can reduce the switching activities on wires that cause crosstalk interferences and high dynamic power. However, data codecs have different overheads in terms of area and performance, and varying capabilities in reducing crosstalk and dynamic power. To adapt to the wide range of processing requirements incurred by applications and operating environments, a reasoning and learning (REAL) framework is proposed for a reconfigurable NoC. REAL dynamically investigates the tradeoffs among reliability, dynamic power reduction, performance, and hardware resource usages to configure the reconfigurable NoC with an appropriate data codec at runtime. As a proof of concept, a 3 × 3 reconfigurable NoC was implemented on Xilinx Virtex-4 field-programmable gate array, which required 8.2% lesser number of slices compared with a conventional NoC. Experiments show that at the same overheads of performance and hardware resources the reconfigurable NoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption.

PRESSNoC: Power-Aware and Reliable Encoding Schemes Supported Reconfigurable Network-on-Chip Architecture

We propose a Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture whereby an encoding can be selected by a REasoning And Learning (REAL) framework at run-time to fit the reliability and power requirements of the application and its execution environment. PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to the traditional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of the traditional architecture by 71%, 32% ,a nd277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. It shows we have higher probability toward the reduction of crosstalk interferences and dynamic power consumption at the same overheads by using the proposed architecture. I. INTRODUCTION Due to advanced process technologies, the decreasing dis- tance between wires has increased the gate count capacity of a chip, but it has also led to significant crosstalk interfer- ences among adjacent wires. Crosstalk is usually caused by undesired conductive coupling from one channel to another. This problem becomes more severe in a Network-on-Chip (NoC) because of the large number of wires used for parallel communication. Further, in advanced process technologies, the ratio of wire to gate power consumption has increased significantly such that the power consumed by wires can no longer be neglected in any power estimation model. Due to the large number of wires in an NoC, the high dynamic power consumption incurred due to parallel communications among concurrently running applications has also become a design issue. To reduce crosstalk interferences and dynamic power con- sumption in an NoC, a well-known and popular method is to reduce the switching activity by means of data encoding schemes which target at reducing the occurrence of spe- cific data patterns such as two/three adjacent transitions and two/three aggressors that may cause crosstalk interferences or high dynamic power consumption. Nevertheless, the tra- ditional encoding methods are fixed, that is, they cannot adapt to the varying requirements of different applications, domains, and systems. The proposed infrastructure mainly includes a novel reconfigurable NoC architecture design, called Power- aware and Reliable Encoding Schemes Supported reconfig- urable Network-on-Chip (PRESSNoC), four data encoding strategies, and an intelligent strategy selection method with reasoning and learning. PRESSNoC supports the dynamic reconfiguration (9) of encoding methods to fit the require- ments of the working set of applications connected to it. The encoding methods include DUal Cycle Encoding (DUCE), Transition and Aggressor reduced Encoding (TAE), Single Additional Flit Encoding (SAFE), and Dual Additional Flit Encoding (DAFE), which differ in the provision of reliability, power efficiency, hardware resource overhead, and perfor- mance overhead. The encoding strategy selection in PRESS- NoC is achieved through a REasoning And Learning (REAL) framework that can dynamically investigate the tradeoffs among reliability requirements, power reduction requirements, performance overhead, and hardware resource utilization. The rest of the paper is organized as follows. Section II summarizes the state-of-the-art reconfigurable NoC designs. In Section III, we describe the proposed encoding strategies with a REAL framework. Experiment results are shown in Section IV. Finally, we conclude in Section V with some future work.

A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability

Due to advanced process technologies the decreasing distance between wires has led to significant bus interferences that introduce crosstalk delay and noise. We first propose two encoding schemes, namely DUCE and GASIE, that can reduce crosstalk delay and noise on the bus lines. The DUCE scheme is a temporal encoding so it needs no additional bits to implement. It can be easily used in existing systems without additional modification in the hardware architecture. For improving performance, we propose a spatial encoding scheme called GASIE which has shielding lines protection and additional bits for transmitting control signals. Compared to existing spatial encoding methods, GASIE not only does not need any profiling information, but also achieves better results. Finally, we combine DUCE and GASIE into a novel spatio-temporal adaptive encoding (STAE) to tradeoff between performance and reliability. The experimental results for various applications showed significant reductions in the number of patterns that were most likely to produce crosstalk delay and errors. The two adjacent transitions and the aggressors can be completely eliminated in the DUCE scheme. While the GASIE scheme can achieve up to 59.9% average reduction of two aggressors, the STAE scheme gives a strongly error tolerant environment of 70% reduction in aggressors and adjacent transitions at the cost of 10% performance loss.