Jim Aarestad

HELP: A Hardware-Embedded Delay PUF

Physical Unclonable Functions enable a secure alternative method to traditional key storage and authentication schemes. This paper presents a novel PUF design that utilizes the existing path delays of a design to generate a random and stable bitstring of desired length with minimal area and performance overhead.

Modular FPGA-based software defined radio for CubeSats

In this paper, we present an adaptive digital communication system using field programmable gate array (FPGA) technology. This system adapts the Universal Software Radio Peripheral (USRP) to better suit the space and power limitations of the CubeSat satellite form factor and the Space Plug-and-Play Avionics (SPA) protocol. The result is a highly-adaptive, plug and play software-defined radio (SDR) that is easily incorporated into any CubeSat design.

ASIC implementation of a hardware-embedded physical unclonable function

Within-die variations in path delays are increasing with scaling. Although higher levels of within-die delay variations are undesirable from a design perspective, they represent a rich source of entropy for applications that make use of ‘secrets’, such as authentication, hardware metering and encryption. Physical unclonable functions or PUFs are a class of circuit primitives that leverage within-die variations as a means of generating random bitstrings for these types of applications. In this study, the authors present test chip results of a hardware-embedded delay PUF (HELP) that extracts entropy from the stability characteristics and within-die variations in path delays. HELP obtains accurate measurements of path delays within core logic macros using an embedded test structure called regional delay behaviour (REBEL). REBEL provides capabilities similar to an off-chip logic analyser, and allows very fast analysis of the temporal behaviour of signals emerging from paths in a core logic macro. Statistical characteristics related to the randomness, reproducibility and uniqueness of the bitstrings produced by HELP are evaluated across industrial-level temperature and supply voltage variations.

Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF

Cryptographic and authentication applications in application-specific integrated circuits (ASICs) and FPGAs, as well as codes for the activation of on-chip features, require the use of embedded secret information. The generation of secret bitstrings using physical unclonable functions, or PUFs, provides several distinct advantages over conventional methods, including the elimination of costly non-volatile memory, and the potential to increase the number of random bits available to applications. In this paper, we propose a Hardware-Embedded Delay PUF (HELP) that is designed to leverage path delay variations that occur in the core logic macros of a chip to create random bitstrings. The bitstrings produced by a set of 30 FPGA boards are evaluated with regard to several statistical quality metrics including uniqueness, randomness, and stability. The stability characteristics of the bitstrings are evaluated by subjecting the FPGAs to commercial-level temperature and supply voltage variations. In particular, we evaluate the reproducibility of the bitstrings generated at 0°C, 25°C, and 70°C, and at nominal and ±10% of the supply voltage. An error avoidance scheme is proposed that provides significant improvement against bit-flip errors in the bitstrings.

Reconfigurable power management using novel monolithically integrated CMOS-on-PV switch

This paper presents a novel reconfigurable power management architecture for PV modules. This architecture allows for operation or isolation (islanding) of individual or groups of cells. Flexible Voc and Isc combinations may be achieved with switching speeds up to 1MHz. Multiple advantages and functionalities can be achieved, such as lower power losses if one cell is shaded or degrading, variable optimized maximum power point tracking, integrated monitoring and communication from PV modules, longer lifetime and others. In order to properly understand the benefits of cell-level switching, bypassing and MPPT, a simulation framework was developed using NGSPICE and Octave which allows component-level simulation of PV modules.