Jin-Fa Lin

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered xor/xnor designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-mum process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an and function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor and gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52.

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively.

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications is presented. By using a wired or scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops (FFs). Since the number of transistor stacking between the power rails is kept at merely two, the proposed design is sustainable to low VDD operations (531 MHz at 0.6 V VDD) for the power saving purpose. Simulation results show that compared with two classic E-TSPC based designs in 0.18 m process technology, as much as 16.4% in operation speed and 39% in power-delay-product can be achieved by the proposed design.

Low power 10-transistor full adder design based on degenerate pass transistor logic

A low power, low complexity full adder design based on degenerate pass transistor logic (PTL) is described. The design kernel is a logically degenerate 5-transistor XOR-XNOR module supporting complementary outputs. In spite of the logic deficiency, this module functions properly in the context of full adder applications. The threshold loss problem common in most PTL designs can be alleviated due to the availability of complementary control signals. Combining this module with multiplexing modules, a novel full adder design using as few as 10 transistors us derived. The proposed full adder design features the least output signal degradation and the smallest Vdd operations against other 10-T counterpart designs. The performance edges in speed, power and power-delay product are also proved via post layout simulations.

Low Power Multipliers Using Enhenced Row Bypassing Schemes

In this paper, we proposed two novel low power multipliers based on enhanced row bypassing schemes. The essence of the power saving idea is eliminating unnecessary computation via signal bypassing. In an array multiplier, futile computations occur on those columns or rows of adder corresponding to zero bits in the input operands. Previous designs resort to input gating and output multiplexing to accomplish signal bypassing. The proposed designs, however, successfully resolve the adverse DC power consumption problem due to voltage loss in gated signals and implement the multiplexing mechanism cleverly via clock CMOS (C2MOS) circuitry. Two versions of the design are proposed with one emphasizing on maximizing power saving and the other focusing on reduced circuit complexity. The circuit overheads of both designs are confined to 23.4% and 12.8%, respectively. The proposed designs also achieve better and consistent power saving than previous work under a wide range of Vdd and the power saving can be as high as 17%.

Low Complexity Dual-Mode Pulse Generator Designs

Two novel low complexity dual-mode pulse generator designs suitable for FFs with triggering mode control are presented. The proposed designs successfully integrate XOR/OR (AND/XNOR) functions into a unified pass transistor logic (PTL) module to provide control on single-or double-edge operations. The designs use as few as 8 transistors each and ingeniously avoid the signal degradation problem inherent in most PTL circuits. As the only dual-mode designs so far, the proposed designs also outperform rival single-mode designs in both aspects of circuit complexity and power consumption.

A high speed and energy efficient full adder design using complementary & level restoring carry logic

In this paper, we propose a low complexity full adder design (10-transistor per bit) featuring higher computing speed, lower operating voltage, and lower energy consumption compared with peer designs. The design adopts inverter buffered XOR/XNOR designs to alleviate the threshold voltage loss problem, which often prevents the full adder design from low supply voltage operation and from direct cascading. The proposed design successfully embeds the buffering circuit in the full adder design so as to enhance the speed performance while keeping the transistor count as minimum. For performance comparison, both DC and AC performances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35mum process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using 10 transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases

Low Power Multiplier Designs Based on Improved Column Bypassing Schemes

In this paper, we proposed two novel low power multiplier designs based on improved column bypassing schemes. The power saving comes from bypassing signals along those adder columns in the array multiplier corresponding to zero bits in the multiplicand. Spurious signal switching activities can then be eliminated when bypassing occurs. The proposed designs successfully resolve the adverse DC power consumption problem in previous research due to troublesome tri-state input buffers. Our designs also implement the bypassing logic cleverly via C2MOS circuitry and eliminate the costly (both circuit and power-wise) multiplexers. The circuit overheads of the proposed designs can be as low as 10% compared with 54% in M. C. Wen et al. (2005). Simulations results also indicate previous work may fail to gain any power saving (and actually deteriorate power consumption) when Vdd is higher than 1.6V. Our designs, nonetheless, achieve power saving consistently in different working conditions and the best saving can be as much as 29%

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master–slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and complementary pass-transistor logic. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high power and delay performance. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. In this design, a virtual