Jin Ge

Active inductor shunt peaking in high-speed VCSEL driver design

An all-transistor active-inductor shunt-peaking structure has been used in a prototype of 8 Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25 μm Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all-transistor active-inductor shunt-peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been taped out, and the prototype has been proven by the preliminary electrical test results and bit error ratio test results. The driver achieves 8 Gbps data rate as simulated with the peaking. We present the all-transistor active-inductor shunt-peaking structure, simulation and test results in this paper.

The Improved Design of Multi-channel Thin Gap Chamber Simulation Signal Source for the ATLAS Detector Upgrade

We develop an improved design of thin gap chamber (TGC) simulation signal source. To further simulate the feature of TGC detector, a novel thought is proposed. The TGC source has 256 channels. Every channel can randomly output the signal in 25 ns. The design is based on true random number generator (TRNG). Considering the electrical connection between the TGC source and the developing trigger electronics, the GFZ connector is used. The experimental results show that the improved TGC simulation signal source can uniformly output the random signal in every channel. The output noise is less than 3 mVrms.

A FPGA-based pulse pile-up rejection technique for the spectrum measurement in PGNAA

In this paper, a FPGA-based pulse pile-up rejection method for the high count rate gamma spectrometer of PGNAA is reported. By using fast peak seeking and feedback control, the pulse width can be narrowed then the pile-up events will be reduced. Test results shown that the energy resolution of the spectrometer is closed to the commercial products. For a count rate of 400 kHz, the number of pile-up events is reduced by 15.84%. This method is easy to implement in FPGAs for real-time data processing.

An FPGA-Based Pulse Pile-up Rejection Technique for Photon Counting Imaging Detectors*

A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. The method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate (MCP) stack, and a wedge and strip anode (WSA). The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140 μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection.