Jin-seok Hong

54x54-bit radix-4 multiplier based on modified booth algorithm

In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 28-2, 27-2, ..., and 10-2 compressors, and XOR based adder are proposed. While the whole design is coded in Verilog-HDL language and implemented through commercially available EDA tool chain, the implementation gives comparable results to full custom designs [1][2]. Realistic simulations using extracted timing parameters from the layout show that the propagation time of a critical path is 3.25ns at 2.5V on a 0.18um process technology, which is almost 21% faster than the conventional multiplier [2].

A 0.18 /spl mu/m CMOS front-end processor for a blu-ray disc recorder with an adaptive PRML

A single-chip front-end SoC, comprising a PRML with an adaptive equalizer, a data processor including a modem and error-correcting code and digital servo with a 16 b DSP, is for Blu-ray disc application. The chip dissipates 0.9 W at 1.8 V and 132 MHz, contains 12M transistors and occupies 50 mm/sup 2/ in 0.18 /spl mu/m CMOS technology.