Jin-Su Jung

An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing

A number of recent efforts have been made to speed up H.264 intra frame coding. When these algorithms are implemented by dedicated hardware accelerators, these hardware resources are often wasted if intra predictions and reconstructions for 4times4 blocks are serialized. In order to avoid a hardware waste, this paper proposes a pipelined execution of the intra predictions and reconstructions of 4times4 blocks. The processing orders of 4times4 intra predictions are derived for both encoding and decoding, respectively, to reduce the dependencies between consecutively processed blocks and minimize pipeline stalls. The proposed pipelined execution of 4times4 intra predictions for encoding is integrated with the other intra frame encoding operations with an efficient scheduling that allows these other operations to be executed in parallel with intra prediction. When compared with the best previous work for intra frame coding (Suh et al., 2005), the execution time is decreased by 41 % even with reduced hardware resources

A Real-Time H.264/AVC Encoder With Complexity-Aware Time Allocation

This paper presents a novel processing time control algorithm for a hardware-based H.264/AVC encoder. The encoder employs three complexity scaling methods partial cost evaluation for fractional motion estimation (FME), block size adjustment for FME, and search range adjustment for integer motion estimation (IME). With these methods, 12 complexity levels are defined to support tradeoffs between the processing time and compression efficiency. A speed control algorithm is proposed to select the complexity level that compresses most efficiently among those that meet the target time budget. The time budget is allocated to each macroblock based on the complexity of the macroblock and on the execution time of other macroblocks in the frame. For main profile compression, an additional complexity scaling method called direction filtering is proposed to select the prediction direction of FME by comparing the costs resulting from forward and backward IMEs. With direction filtering in addition to the three complexity scaling methods for baseline compression, 32 complexity levels are defined for main profile compression. Experimental results show that the speed control algorithm guarantees the processing time to meet the given time budget with negligible quality degradation. Various complexity levels for speed control are also used to speed up the encoding time with a slight degradation in quality and a minor reduction of the compression efficiency.

Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications

H.264/AVC adopts aggressive compression algorithms at the cost of increased computational complexity. To speed up the H.264/AVC intraframe coding, this paper proposes two novel techniques: early termination and pipelined execution. In P slices, intra 4×4 and 16×16 predictions are early terminated with the threshold determined by the cost of motion estimation. In I slices, intra 4×4 prediction is early terminated with the threshold derived from intra 16×16 prediction. The threshold function is chosen as a monotonically decreasing linear function with its optimal coefficients determined by experiments. For the pipelined execution of 4×4 intrapredictions, the processing order of 4×4 blocks is changed to reduce the dependencies between consecutively processed blocks. In I slices, computation for 4×4 intraprediction is reduced by 19 percent with the proposed early termination. In P slices, computations for 4×4 and 16×16 intrapredictions are reduced by more than 81 and 91 percents, respectively. The pipelined execution reduces the computation time by 41 percent. In spite of the speed-up by the proposed methods, degradation in rate-distortion performance is negligible. The proposed pipelined execution is integrated with other H.264/AVC hardware accelerators and fabricated as an SoC using Dongbu 0.13 μm technology.

An SoC integrating an H.264 encoder with an ISP

The SoC presented in this paper integrates an H.264 encoder with an ISP (Image Signal Processor). It is currently implemented in an FPGA and processes an HD-size (1280 × 720) image at the speed of 15 fps with the operating clock frequency of 50 MHz. In the presented demo system, a Bayer input from a CMOS image is given to the FPGA and the output stream is transmitted through an USB transceiver to a PC that decodes and displays the H.264 stream.

A synchronous DRAM controller for an H.264/AVC encoder

In order to use a synchronous dynamic RAM (SDRAM) as the off-chip memory of an H.264/AVC encoder, this paper proposes an efficient SDRAM memory controller with an asynchronous bridge. With the proposed architecture, the SDRAM bandwidth is increased by making the operation frequency of an external SDRAM higher than that of the hardware accelerators of an H.264/AVC encoder. Experimental results show that the encoding speed is increased by 30.5% when the SDRAM clock frequency is increased from 100 MHz to 200 MHz while the H.264/AVC hardware accelerators operate at 100 MHz.

Fast pipeline schedule for an H.264 intra frame encoder with early termination

This paper presents a fast H.264 intra frame encoder that processes an HD720p size video at 30 fps with the operating clock frequency of 40 MHz. The low clock frequency is achieved by a novel intra prediction schedule that employs pipelining of the 4×4 predictions and the early termination of 16×16 prediction. The pipelining is achieved by the optimal processing order for 4×4 predictions that reduces bubbles between consecutive 4x4 predictions. Execution cycles of 16×16 prediction are reduced by early termination which uses the cost of 4×4 prediction as the stop condition. With the proposed schedule, the execution time of 16×16 prediction is saved by 49% for intra prediction of HD720p size videos. For further speed-up, the two least probable modes among nine 4×4 prediction modes are excluded. As a result, the required execution time is reduced to 370 cycles which are about 61 cycles faster than the previous best implementation.

Speed control for a hardware based H.264/AVC encoder

This paper proposes a novel processing time control algorithm for a hardware-based H.264/AVC encoder. In the proposed speed control, a macroblock processing time budget is allocated adaptively according to the processing time of the other blocks. Then, twelve complexity levels are defined to provide various combinations of processing time and compression efficiency. For a given time budget, the algorithm selects the proper complexity level that compresses most efficiently among the levels that meet the time budget. Experimental results show that real-time processing is achieved by the speed control with negligible quality degradation while between 31.2% and 50% macroblocks violates its time budget without speed control.