Jin-Tai Yan

Low-power multiplier design with row and column bypassing

Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2-dimensional bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the power dissipation with only 15% hardware overhead on the average for 4×4, 8×8 and 16×16 multipliers.

Low-cost low-power bypassing-based multiplier design

Based on the simplification of the addition operations in a low-power bypassing-based multiplier, a low-cost low-power bypassing-based multiplier is proposed Compared with row-bypassing multiplier, column-bypassing multiplier and 2-dimensional bypassing-based multiplier for 20 tested examples, the experimental results show that our proposed low-cost low-power multiplier saves 15.1% of hardware cost and reduces 29.6% of the power dissipation on the average for 4×4, 8×8 and 16×16 multipliers.

Electromigration-aware rectilinear Steiner tree construction for analog circuits

In this paper, given a set of n terminals including some current sources and some current sinks in a signal net, the maximum current density and the minimum wire width, a current-driven routing tree can be constructed to satisfy the current flow in Kirchhoffpsilas current laws. Furthermore, all the area-driven Steiner points are assigned to reduce the total wiring area based on the determination of current-driven wire widths. Finally, an electromigration-aware rectilinear Steiner tree (ERST) is constructed by assigning all the physical paths with current driven wire widths. Compared with the Lienigpsilas approach[7], the experimental results show that our proposed approach reduces 5.3%~10.4% total routing area for tested examples in reasonable CPU time.

Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis

In this paper, based on probabilistic via-connection analysis of single vias and redundant vias, it is well known that on-track redundant via insertion is more important and critical than off-track redundant via insertion for yield optimization. Furthermore, a two-phase insertion approach for yield optimization is proposed to insert on-track redundant vias by finding a maximum matching result in a bipartite graph and insert off-track redundant vias by using a maximum constrained edge-pair matching result in a constrained edge-pair matching with via-sharing constraints. According to the Poisson yield model for redundant via insertion, the experimental results show that our proposed two-phase insertion approach can increase 0.3%~7.4% wirelength to improve 4.3%~44.8% chip yield for the tested benchmarks.

Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation

The dynamic structure of a hierarchical stair contour is firstly proposed to maintain an incremental floorplan contour for the placement of a sequence of given blocks. Based on the LB-packing process of any given block in a compact floorplan, a double-bound list (DBL) is further proposed to represent the geometrical adjacent relations in a compact floorplan. Finally, an SA-based approach based on the combination of one rectangular-packing process and one LB-packing process as one perturbation operation is proposed to allocate and integrate the possible decaps of all the blocks into the original floorplan. Experimental results show that our proposed SA-based allocation approach based on DBL representation obtains very promising results for MCNC benchmark circuits.

Thermal via planning for temperature reduction in 3D ICs

In this paper, based on the temperature calculation in block-level thermal model, a two-phase approach is proposed to reduce the final floorplan temperature by redistributing the white space in all the device layers and inserting the thermal vias onto the available white space. The experimental results show that our proposed approach reduces 5.5%, 11.3% and 20.5% of temperature on 100%, 110% and 120% floorplan regions in reasonable CPU time for ten GSRC benchmarks on the average, respectively.

Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points

In this paper, given a set of connecting nodes in a signal net, based on the concept of movable Steiner points and the dining-driven flexibility of a Steiner point, it is assumed that all the Steiner points are initially hidden inside the connecting nodes in a shortest-path tree (SPT). An effective timing-driven rectilinear Steiner tree (TRST) approach is proposed to obtain a timing-driven rectilinear Steiner tree by introducing hidden Steiner points in a SPT onto feasible positions. The experimental results show that our proposed TRST approach obtains better timing-driven Steiner trees than the MVERT approach for the tested signal nets.

Timing-constrained yield-driven redundant via insertion

In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach can further reduce 0.006% total wire length on the average with the reduction of 0.0002% chip yield to maintain 100% timing constraints for the tested benchmarks.

Utilization of multi-bit flip-flops for clock power reduction

Utilization of multi-bit flip-flops in a synchronous design has been becoming a significant methodology for clock power reduction. However, some published approaches are usually based on the assumption that the bit number of the flip-flops is continuous or the number of the available flip-flops is infinite in a cell library. Under the physical limitation of the flip-flop cells in a real cell library, the bit number of the flip-flops is discrete and the number of the available flip-flops is finite. In this paper, given a synchronous system with a set of 1-bit flip-flops in a placement plane, the timing constraints of the associated signals in the flip-flops and the available flip-flops in a real cell library, based on the bit number of the available multi-bit flip-flops in the given cell library, an optimal approach is proposed to obtain the maximum power-saving result by merging 1-bit flip-flops into the available flip-flops. Compared with the original synchronous designs using 1-bit flip-flops, the experimental results show that our proposed approach reduces 38.4% of the flip-flop area and saves 24.9% of the clock power to maintain the synchronous property on the average for five tested examples in reasonable CPU time.

Thermal-driven white space redistribution for block-level floorplans

Given an LB-compact floorplan, a 3D block-level thermal model is firstly proposed to calculate the temperature of each circuit block in reasonable time. Furthermore, based on the temperature calculation in the proposed 3D block-level thermal model and the final floorplan region, an iterative approach is proposed to reduce the final floorplan temperature by inserting or redistribution the feasible white space. The experimental results show that our proposed iterative approach obtains very promising temperature reduction in reasonable CPU time for MCNC benchmarks.